公开(公告)号：US08811069B2

公开(公告)日：2014-08-19

申请号：US13591696

申请日：2012-08-22

申请人： Gyu Hong Kim ,  Jong Hoon Jung

发明人： Gyu Hong Kim ,  Jong Hoon Jung

IPC分类号： G11C11/00

CPC分类号： G11C7/22 ,  G11C7/08 ,  G11C11/41 ,  G11C11/419 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012

摘要： The memory device includes a memory cell array, an access control circuit configured to access the memory cell array, a control signal generation circuit configured to generate a control signal for controlling an operation of the access control circuit, and a variable delay circuit configured to generate a delay signal by variably delaying a clock signal according to an external signal. The control signal generation circuit adjusts an activation timing of the control signal in response to the delay signal.

摘要翻译： 存储装置包括：存储单元阵列，被配置为存取存储单元阵列的访问控制电路;控制信号生成电路，被配置为产生用于控制访问控制电路的操作的控制信号;以及可变延迟电路， 通过根据外部信号可变延迟时钟信号的延迟信号。 控制信号发生电路根据延迟信号调整控制信号的激活定时。

公开(公告)号：US09299711B2

公开(公告)日：2016-03-29

申请号：US14032769

申请日：2013-09-20

申请人： Tae Joong Song ,  Gyu Hong Kim ,  Jae Ho Park ,  Jong Hoon Jung

发明人： Tae Joong Song ,  Gyu Hong Kim ,  Jae Ho Park ,  Jong Hoon Jung

IPC分类号： H01L29/78 ,  H01L27/11 ,  H01L29/417 ,  G11C11/419 ,  G11C11/412

CPC分类号： H01L27/1104 ,  G11C11/412 ,  G11C11/419 ,  H01L29/41791 ,  H01L29/785

摘要： A fin Field Effect Transistor (finFET) can include a source region and a drain region of the finFET. A gate of the finFET can cross over a fin of the finFET between the source and drain regions. First and second silicide layers can be on the source and drain regions respectively. The first and second silicide layers can include respective first and second surfaces that face the gate crossing over the fin, where the first and second surfaces are different sizes.

摘要翻译： 鳍状场效应晶体管（finFET）可以包括finFET的源极区域和漏极区域。 finFET的栅极可以跨越源极和漏极区域之间的finFET的鳍。 第一和第二硅化物层可以分别在源区和漏区上。 第一和第二硅化物层可以包括面对栅极的相应的第一和第二表面，其中第一和第二表面是不同的尺寸。

公开(公告)号：US20140085966A1

公开(公告)日：2014-03-27

申请号：US14032769

申请日：2013-09-20

申请人： Tae Joong Song ,  Gyu Hong Kim ,  Jae Ho Park ,  Jong Hoon Jung

发明人： Tae Joong Song ,  Gyu Hong Kim ,  Jae Ho Park ,  Jong Hoon Jung

IPC分类号： H01L27/11 ,  G11C11/419

CPC分类号： H01L27/1104 ,  G11C11/412 ,  G11C11/419 ,  H01L29/41791 ,  H01L29/785

摘要： A fin Field Effect Transistor (finFET) can include a source region and a drain region of the finFET. A gate of the finFET can cross over a fin of the finFET between the source and drain regions. First and second silicide layers can be on the source and drain regions respectively. The first and second silicide layers can include respective first and second surfaces that face the gate crossing over the fin, where the first and second surfaces are different sizes.

摘要翻译： 鳍状场效应晶体管（finFET）可以包括finFET的源极区域和漏极区域。 finFET的栅极可以跨越源极和漏极区域之间的finFET的鳍。 第一和第二硅化物层可以分别在源区和漏区上。 第一和第二硅化物层可以包括面对栅极的相应的第一和第二表面，其中第一和第二表面是不同的尺寸。

公开(公告)号：US06563756B2

公开(公告)日：2003-05-13

申请号：US09993770

申请日：2001-11-27

申请人： Gyu Hong Kim

发明人： Gyu Hong Kim

IPC分类号： G11C700

CPC分类号： G11C11/406

摘要： A memory device capable of reducing refresh noise generated in refreshing a plurality of memory cell blocks at the same time is provided. The memory device includes a plurality of memory cell blocks, a block select unit, and a row decoder. Each of memory cell blocks includes a plurality of sub-memory cell array blocks, and the block select unit outputs a plurality of block select signals corresponding to a plurality of control signals generated by a block select address. The row decoder selects at least one memory cell block corresponding to at least one block select signal activated among the plurality of the block select signals and activates a word line of a memory cell block selected by responding to a row address.

摘要翻译： 提供了能够同时减少刷新多个存储单元块时产生的刷新噪声的存储器件。 存储器件包括多个存储单元块，块选择单元和行解码器。 每个存储单元块包括多个子存储单元阵列块，并且块选择单元输出与由块选择地址生成的多个控制信号对应的多个块选择信号。 行解码器选择与在多个块选择信号中激活的至少一个块选择信号相对应的至少一个存储单元块，并激活通过响应行地址而选择的存储单元块的字线。

公开(公告)号：US06330199B2

公开(公告)日：2001-12-11

申请号：US09741162

申请日：2000-12-21

申请人： Hyun Taek Jung ,  Gyu Hong Kim

发明人： Hyun Taek Jung ,  Gyu Hong Kim

IPC分类号： G11C700

CPC分类号： G11C29/808 ,  G11C29/846

摘要： In a semiconductor memory device having redundancy capability, a control signal generating circuit is included respectively for each of a predetermined number of redundant column select signal lines, to generate a predetermined number of block control signals by dividing a plurality of memory cell array blocks into a predetermined number of groups. A predetermined number of defective enable signal generating circuits are included for each of the redundant column select signal lines, to generate a predetermined number of redundant enable signals when defective addresses are input. The redundant column select signal lines are established for defective addresses based on the block control signals. A selection circuit is included respectively for each of the redundant column select signal lines to generate a select signal for selecting a redundant column select signal line corresponding to each of a predetermined number of redundant enable signals, in response to the block control signals. The efficiency of redundancy is thus improved by performing a redundancy operation by dividing a plurality of memory cell arrays into a predetermined number of groups for each of redundant column select signals.