Method and apparatus for run length limited TMDS-like encoding of data
    1.
    发明授权
    Method and apparatus for run length limited TMDS-like encoding of data 有权
    运行长度限制的方法和装置TMDS类似的数据编码

    公开(公告)号:US06897793B1

    公开(公告)日:2005-05-24

    申请号:US10835301

    申请日:2004-04-29

    IPC分类号: H03M5/14 H03M7/00

    CPC分类号: H03M5/145

    摘要: A serial data transmission system in which a transmitter encodes data in accordance with a TMDS-like encoding algorithm and transmits the TMDS-like encoded data over a serial link to a receiver. The encoded data are transmitted as a run length limited (“RLL”) code word sequence, including transition-minimized code words. In some embodiments, the RLL code word sequence includes only Min words, including both DC balancing Min words and DC unbalancing Min words. In other embodiments, the RLL code word sequence includes both transition-maximized code words and transition-minimized code words. Other aspects of the invention are circuitry and methods for TMDS-like encoding of data for transmission as an RLL code word sequence.

    摘要翻译: 一种串行数据传输系统,其中发射机根据TMDS编码算法对数据进行编码,并通过串行链路将TMDS类编码数据发送到接收机。 编码数据作为游程长度限制(“RLL”)码字序列发送,包括转换最小化码字。 在一些实施例中,RLL码字序列仅包括最小字,包括直流平衡最小字和直流不平衡最小字。 在其他实施例中,RLL码字序列包括转换最大化码字和转换最小码字。 本发明的其他方面是用于作为RLL码字序列传输的数据的TMDS类编码的电路和方法。

    Mechanism for low power standby mode control circuit
    2.
    发明授权
    Mechanism for low power standby mode control circuit 有权
    低功耗待机模式控制电路机制

    公开(公告)号:US09015509B2

    公开(公告)日:2015-04-21

    申请号:US13362930

    申请日:2012-01-31

    IPC分类号: G06F1/32

    摘要: Embodiments of the invention are generally directed to a low power standby mode control circuit. An embodiment of an apparatus includes a processor, an interface for a connection with a second apparatus, and an operational circuit, wherein the processor is to disable one or more power connections to the operational circuit in a standby mode. The apparatus further includes a standby mode control circuit, the standby control circuit to operate using a standby power source, wherein the standby mode control circuit is to detect a stimulus signal from the second apparatus and in response to the stimulus signal the standby control circuit is to signal the processor, the processor to enable the one or more power connections of the operational circuit.

    摘要翻译: 本发明的实施例通常涉及低功率待机模式控制电路。 装置的实施例包括处理器,用于与第二装置的连接的接口和操作电路,其中处理器在待机模式下禁用与操作电路的一个或多个电源连接。 该设备还包括备用模式控制电路,待机控制电路使用待机电源进行操作,其中待机模式控制电路将检测来自第二设备的激励信号,并且响应于激励信号,备用控制电路为 为了向处理器发信号,处理器启用操作电路的一个或多个电源连接。

    MECHANISM FOR LOW POWER STANDBY MODE CONTROL CIRCUIT
    3.
    发明申请
    MECHANISM FOR LOW POWER STANDBY MODE CONTROL CIRCUIT 有权
    低功耗待机模式控制电路的机理

    公开(公告)号:US20120204048A1

    公开(公告)日:2012-08-09

    申请号:US13362930

    申请日:2012-01-31

    IPC分类号: G06F1/32

    摘要: Embodiments of the invention are generally directed to a low power standby mode control circuit. An embodiment of an apparatus includes a processor, an interface for a connection with a second apparatus, and an operational circuit, wherein the processor is to disable one or more power connections to the operational circuit in a standby mode. The apparatus further includes a standby mode control circuit, the standby control circuit to operate using a standby power source, wherein the standby mode control circuit is to detect a stimulus signal from the second apparatus and in response to the stimulus signal the standby control circuit is to signal the processor, the processor to enable the one or more power connections of the operational circuit.

    摘要翻译: 本发明的实施例通常涉及低功率待机模式控制电路。 装置的实施例包括处理器,用于与第二装置的连接的接口和操作电路,其中处理器在待机模式下禁用与操作电路的一个或多个电源连接。 该设备还包括备用模式控制电路,待机控制电路使用待机电源进行操作,其中待机模式控制电路将检测来自第二设备的激励信号,并且响应于激励信号,备用控制电路为 为了向处理器发信号,处理器启用操作电路的一个或多个电源连接。

    CURRENT MODE CIRCUITRY TO MODULATE A COMMON MODE VOLTAGE
    4.
    发明申请
    CURRENT MODE CIRCUITRY TO MODULATE A COMMON MODE VOLTAGE 有权
    电流模式电路来调制共模电压

    公开(公告)号:US20090323830A1

    公开(公告)日:2009-12-31

    申请号:US12555300

    申请日:2009-09-08

    CPC分类号: H04L5/20

    摘要: In some embodiments, a chip includes transmitters to transmit differential signals on conductors; and current mode circuitry to selectively modulate a common mode voltage of the differential signals to communicate data. In other embodiments, a system includes a first chip to transmit first and second differential signals on conductors, and a second chip. The second chip includes receivers to receive the first and second differential signals from the conductors and provide received signals representative thereof, and current mode circuitry to selectively modulate a common mode voltage of either the first or second differential signals to communicate data and wherein the first chip includes common mode detection circuitry to detect changes in the common mode voltage. Other embodiments are described and claimed.

    摘要翻译: 在一些实施例中,芯片包括在导体上传输差分信号的发射器; 以及电流模式电路,用于选择性地调制差分信号的共模电压以传送数据。 在其他实施例中,系统包括用于在导体上传输第一和第二差分信号的第一芯片和第二芯片。 第二芯片包括接收器,用于从导体接收第一和第二差分信号并提供表示其的接收信号;以及电流模式电路,用于选择性地调制第一或第二差分信号的共模电压以传送数据,并且其中第一芯片 包括用于检测共模电压变化的共模检测电路。 描述和要求保护其他实施例。

    Current mode circuitry to modulate a common mode voltage
    5.
    发明授权
    Current mode circuitry to modulate a common mode voltage 有权
    用于调制共模电压的电流模式电路

    公开(公告)号:US07589559B2

    公开(公告)日:2009-09-15

    申请号:US11643388

    申请日:2006-12-20

    IPC分类号: H03K19/0175

    CPC分类号: H04L5/20

    摘要: In some embodiments, a chip includes transmitters to transmit differential signals on conductors; and current mode circuitry to selectively modulate a common mode voltage of the differential signals to communicate data. In other embodiments, a system includes a first chip to transmit first and second differential signals on conductors, and a second chip. The second chip includes receivers to receive the first and second differential signals from the conductors and provide received signals representative thereof, and current mode circuitry to selectively modulate a common mode voltage of either the first or second differential signals to communicate data and wherein the first chip includes common mode detection circuitry to detect changes in the common mode voltage. Other embodiments are described and claimed.

    摘要翻译: 在一些实施例中,芯片包括在导体上传输差分信号的发射器; 以及电流模式电路,用于选择性地调制差分信号的共模电压以传送数据。 在其他实施例中,系统包括用于在导体上传输第一和第二差分信号的第一芯片和第二芯片。 第二芯片包括接收器,用于从导体接收第一和第二差分信号并提供表示其的接收信号;以及电流模式电路,用于选择性地调制第一或第二差分信号的共模电压以传送数据,并且其中第一芯片 包括用于检测共模电压变化的共模检测电路。 描述和要求保护其他实施例。

    Current mode circuitry to modulate a common mode voltage
    6.
    发明申请
    Current mode circuitry to modulate a common mode voltage 有权
    用于调制共模电压的电流模式电路

    公开(公告)号:US20080169838A1

    公开(公告)日:2008-07-17

    申请号:US11643388

    申请日:2006-12-20

    IPC分类号: H01P5/00

    CPC分类号: H04L5/20

    摘要: In some embodiments, a chip includes transmitters to transmit differential signals on conductors; and current mode circuitry to selectively modulate a common mode voltage of the differential signals to communicate data. In other embodiments, a system includes a first chip to transmit first and second differential signals on conductors, and a second chip. The second chip includes receivers to receive the first and second differential signals from the conductors and provide received signals representative thereof, and current mode circuitry to selectively modulate a common mode voltage of either the first or second differential signals to communicate data and wherein the first chip includes common mode detection circuitry to detect changes in the common mode voltage. Other embodiments are described and claimed.

    摘要翻译: 在一些实施例中,芯片包括在导体上传输差分信号的发射器; 以及电流模式电路,用于选择性地调制差分信号的共模电压以传送数据。 在其他实施例中,系统包括用于在导体上传输第一和第二差分信号的第一芯片和第二芯片。 第二芯片包括接收器,用于从导体接收第一和第二差分信号并提供表示其的接收信号;以及电流模式电路,用于选择性地调制第一或第二差分信号的共模电压以传送数据,并且其中第一芯片 包括用于检测共模电压变化的共模检测电路。 描述和要求保护其他实施例。

    Current mode circuitry to modulate a common mode voltage
    7.
    发明授权
    Current mode circuitry to modulate a common mode voltage 有权
    用于调制共模电压的电流模式电路

    公开(公告)号:US07872498B2

    公开(公告)日:2011-01-18

    申请号:US12555300

    申请日:2009-09-08

    IPC分类号: H03K19/0175

    CPC分类号: H04L5/20

    摘要: In some embodiments, a chip includes transmitters to transmit differential signals on conductors; and current mode circuitry to selectively modulate a common mode voltage of the differential signals to communicate data. In other embodiments, a system includes a first chip to transmit first and second differential signals on conductors, and a second chip. The second chip includes receivers to receive the first and second differential signals from the conductors and provide received signals representative thereof, and current mode circuitry to selectively modulate a common mode voltage of either the first or second differential signals to communicate data and wherein the first chip includes common mode detection circuitry to detect changes in the common mode voltage. Other embodiments are described and claimed.

    摘要翻译: 在一些实施例中,芯片包括在导体上传输差分信号的发射器; 以及电流模式电路,用于选择性地调制差分信号的共模电压以传送数据。 在其他实施例中,系统包括用于在导体上传输第一和第二差分信号的第一芯片和第二芯片。 第二芯片包括接收器,用于从导体接收第一和第二差分信号并提供表示其的接收信号;以及电流模式电路,用于选择性地调制第一或第二差分信号的共模电压以传送数据,并且其中第一芯片 包括用于检测共模电压变化的共模检测电路。 描述和要求保护其他实施例。

    Reduced dead-cycle, adaptive phase tracking method and apparatus
    9.
    发明授权
    Reduced dead-cycle, adaptive phase tracking method and apparatus 有权
    减少死循环,自适应相位跟踪方法和装置

    公开(公告)号:US07236553B1

    公开(公告)日:2007-06-26

    申请号:US10763905

    申请日:2004-01-23

    IPC分类号: H04L7/00

    CPC分类号: H04L7/0337 H04L7/0008

    摘要: A data sampling method and circuit employing an oversampling clock to oversample a data signal, a phase tracker for use with or in a data sampling circuit, and a method for identifying a sequence of best sampling positions for sampling a data signal from signal samples generated using an oversampling clock. In some embodiments, data indicative of the phase of at least one of the oversampling clock's sampling positions relative to the center of the data eye are low-pass filtered in a manner determined by the data signal's bit rate. In other embodiments, the number of dead cycles of the phase tracker decision loop is reduced by generating possible solutions in parallel and moving the feedback point so as to occur as late as practical, or the phase tracker ignores a sample set when updating its determination of the best sampling position when the sample set indicates that the data signal has less than a predetermined number of transitions during a corresponding tracking period.

    摘要翻译: 使用过采样时钟对数据信号进行过采样的数据采样方法和电路,与数据采样电路一起使用或在数据采样电路中使用的相位跟踪器,以及用于识别最佳采样位置序列的方法,用于从使用 过采样时钟。 在一些实施例中,指示相对于数据眼睛的中心的过采样时钟的采样位置中的至少一个的相位的数据以由数据信号的比特率确定的方式进行低通滤波。 在其他实施例中,相位跟踪器判定循环的死循环的数量通过并行产生可能的解并且将反馈点移动以便尽可能晚地发生而减少,或者当更新其样本集的确定时,相位跟踪器忽略样本集 当样本集合表示在对应的跟踪周期期间数据信号具有小于预定数量的转换时的最佳采样位置。