公开(公告)号：US06258646B1

公开(公告)日：2001-07-10

申请号：US09149631

申请日：1998-09-08

申请人： H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Derick J. Wristers

发明人： H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Derick J. Wristers

IPC分类号： H01L218238

CPC分类号： H01L27/092 ,  H01L21/823814 ,  Y10S257/90

摘要： A transistor and a transistor fabrication method for forming an LDD structure in which the n-type dopants associated with an n-channel transistor are formed prior to the formation of the p-type dopants is presented. The n-type source/drain and LDD implants generally require higher activation energy (thermal anneal) than the p-type source/drain and LDD implants. The n-type arsenic source/drain implant, which has the lowest diffusivity and requires the highest temperature anneal, is performed first in the LDD process formation. Performing such a high temperature anneal first ensures minimum additional migration of subsequent, more mobile implants. Mobile implants associated with lighter and less dense implant species are prevalent in LDD areas near the channel perimeter. The likelihood of those implants moving into the channel is lessened by tailoring subsequent anneal steps to temperatures less than the source/drain anneal step.

摘要翻译： 提出一种用于形成LDD结构的晶体管和晶体管制造方法，其中在形成p型掺杂剂之前形成与n沟道晶体管相关联的n型掺杂剂。 n型源极/漏极和LDD植入物通常需要比p型源极/漏极和LDD植入物更高的活化能（热退火）。 首先在LDD工艺形成中执行具有最低扩散率并且需要最高温度退火的n型砷源/漏极注入。 首先进行这样的高温退火可确保随后的更多移动式植入物的最小额外迁移。 与更轻和较不密集的种植体物种相关的移植植入物在通道周边附近的LDD区域是普遍的。 通过将后续退火步骤调整到低于源极/漏极退火步骤的温度，使得这些植入物进入通道的可能性降低。

公开(公告)号：US06188114B1

公开(公告)日：2001-02-13

申请号：US09204016

申请日：1998-12-01

申请人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L31119

CPC分类号： H01L29/41783 ,  H01L29/41775 ,  H01L29/66575 ,  H01L29/6659

摘要： An IGFET with metal spacers is disclosed. The IGFET includes a gate electrode on a gate insulator on a semiconductor substrate. Sidewall insulators are adjacent to opposing vertical edges of the gate electrode, and metal spacers are formed on the substrate and adjacent to the sidewall insulators. The metal spacers are electrically isolated from the gate electrode but contact portions of the drain and the source. Preferably, the metal spacers are adjacent to edges of the gate insulator beneath the sidewall insulators. The metal spacers are formed by depositing a metal layer over the substrate then applying an anisotropic etch. In one embodiment, the metal spacers contact lightly and heavily doped drain and source regions, thereby increasing the conductivity between the heavily doped drain and source regions and the channel underlying the gate electrode. The metal spacers can also provide low resistance drain and source contacts.

摘要翻译： 公开了具有金属间隔物的IGFET。 IGFET在半导体衬底上的栅极绝缘体上包括栅电极。 侧壁绝缘体与栅电极的相对的垂直边缘相邻，并且金属间隔件形成在衬底上并且与侧壁绝缘体相邻。 金属间隔物与栅电极电绝缘，但是漏极和源极的接触部分。 优选地，金属间隔件邻近侧壁绝缘体之下的栅极绝缘体的边缘。 通过在衬底上沉积金属层然后施加各向异性蚀刻来形成金属间隔物。 在一个实施例中，金属间隔物接触轻掺杂和重掺杂的漏极和源极区域，从而增加重掺杂漏极和源极区域之间的导电性以及栅电极下面的沟道。 金属间隔物还可以提供低电阻漏极和源极触点。

公开(公告)号：US6166354A

公开(公告)日：2000-12-26

申请号：US876381

申请日：1997-06-16

申请人： Frederick N. Hause ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Frederick N. Hause ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： C30B31/12 ,  C30B31/18 ,  F27B5/14

CPC分类号： C30B31/18 ,  C30B31/12

摘要： An optical monitoring of electrical characteristics of devices in a semiconductor is performed during an anneal step to detect the time annealing is complete and activation occurs. A surface photovoltage measurement is made during annealing to monitor the charge state on the surface of a substrate wafer to determine when the substrate is fully annealed. The surface photovoltage measurement is monitored, the time of annealing is detected, and a selected over-anneal is controlled. The surface photovoltage (SPV) measurement is performed to determine a point at which a dopant or impurity such as boron or phosphorus is annealed in a silicon lattice. In some embodiments, the point of detection is used as a feedback signal in an RTA annealing system to adjust a bank of annealing lamps for annealing and activation uniformity control. The point of detection is also used to terminate the annealing process to minimize D.sub.t.

摘要翻译： 在退火步骤期间执行半导体器件的电特性的光学监测，以检测时间退火完成并发生激活。 在退火期间进行表面光电压测量以监测衬底晶片的表面上的电荷状态，以确定衬底何时完全退火。 监测表面光电压测量，检测退火时间，并控制所选择的过退火。 执行表面光电压（SPV）测量以确定在硅晶格中退火掺杂剂或杂质如硼或磷的点。 在一些实施例中，将检测点用作RTA退火系统中的反馈信号，以调整用于退火和激活均匀性控制的退火灯组。 检测点也用于终止退火过程以最小化Dt。

公开(公告)号：US6146978A

公开(公告)日：2000-11-14

申请号：US73639

申请日：1998-05-06

申请人： Mark W. Michael ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Frederick N. Hause ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Mark W. Michael ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Frederick N. Hause ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L21/768 ,  H01L21/8238 ,  H01L21/44 ,  H01L21/4763 ,  H01L31/119

CPC分类号： H01L21/823871 ,  H01L21/76802 ,  H01L21/76895

摘要： An interlevel interconnect is formed in a window opened through an isolation layer and through an etch barrier to expose an electrode surface and an adjacent isolation barrier. The interlevel interconnect may be disposed on substantially all of a portion of the underlying electrode such as an insulated gate field effect transistor (IGFET) source/drain region surface. The etch barrier provides controlled etching to allow for overlap of the interlevel interconnect onto the isolation barrier without increased parasitic capacitance relative to conventional contact misalignments. Furthermore, allaying concerns of overlapping allows for increased utilization of source/drain region surface area by the interlevel interconnect. Furthermore, the etch barrier allows the interlevel interconnect to strap electrodes of a plurality of circuit devices while exhibiting nominal if any substrate to interlevel interconnect leakage currents.

摘要翻译： 在通过隔离层打开的窗口中并通过蚀刻屏障形成层间互连，以露出电极表面和相邻隔离屏障。 层间互连可以布置在底层电极的基本上全部的一部分上，例如绝缘栅场效应晶体管（IGFET）源/漏区表面。 蚀刻屏障提供受控的蚀刻，以允许层间互连重叠在隔离屏障上，而不增加寄生电容，相对于传统的接触不对准。 此外，消除重叠的关注允许通过层间互连增加源/漏区表面积的利用。 此外，蚀刻屏障允许层间互连以多个电路器件的带状电极同时显示标称的任何衬底以互连互连漏电流。

公开(公告)号：US6104063A

公开(公告)日：2000-08-15

申请号：US942998

申请日：1997-10-02

申请人： H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Derick J. Wristers

发明人： H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Derick J. Wristers

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/76 ,  H01L27/088

CPC分类号： H01L29/66492 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S257/90

摘要： A transistor and a transistor fabrication method are presented where a sequence of spacers are formed and partially removed upon sidewall surfaces of the gate conductor to produce a graded junction having a relatively smooth doping profile. The spacers include removable and non-removable structures formed on the sidewall surfaces. The adjacent structures have dissimilar etch characteristics compared to each other and compared to the gate conductor. A first dopant (MDD dopant) and a second dopant (source/drain dopant) are implanted into the semiconductor substrate after the respective formation of the removable structure and the non-removable structure. A third dopant (LDD dopant) is implanted into the semiconductor substrate after the removable layer is removed from between the gate conductor and the non-removable structure (spacer). As a result a graded junction is created having higher concentration regions formed outside of lightly concentration regions, relative to the channel area. Such a doping profile provides superior protection against the hot-carrier effect compared to the traditional LDD structure. The smoother the doping profile, the more gradual the voltage drop across the channel/drain junction. A more gradual voltage drop gives rise to a smaller electric field and reduces the hot-carrier effect. Furthermore, the MDD and source/drain implants are performed first, prior to the LDD implant. This allows high-temperature thermal anneals to be performed first, followed by lower temperature anneals second.

摘要翻译： 提出了晶体管和晶体管制造方法，其中在栅极导体的侧壁表面上形成并部分地去除间隔物序列，以产生具有相对平滑的掺杂分布的梯度结。 间隔件包括形成在侧壁表面上的可移除和不可移除的结构。 相邻的结构具有彼此相比的不同的蚀刻特性并且与栅极导体相比较。 在可移除结构和不可移除结构的相应形成之后，将第一掺杂剂（MDD掺杂剂）和第二掺杂剂（源极/漏极掺杂剂）注入到半导体衬底中。 在可移除层从栅极导体和不可移除结构（间隔物）之间移除之后，将第三掺杂剂（LDD掺杂剂）注入到半导体衬底中。 结果，相对于通道面积产生了在轻微浓度区域之外形成的具有较高浓度区域的分级结。 与传统的LDD结构相比，这种掺杂分布提供了优于热载体效应的保护。 掺杂曲线越平滑，通道/漏极结上的电压降越低。 更加缓慢的电压降会导致较小的电场并降低热载流子效应。 此外，在LDD植入之前，首先执行MDD和源/漏植入。 这允许首先执行高温热退火，其次是较低的温度退火。

公开(公告)号：US6096639A

公开(公告)日：2000-08-01

申请号：US056835

申请日：1998-04-07

申请人： Robert Dawson ,  Mark I. Gardner ,  Frederick N. Hause ,  H. Jim Fulford, Jr. ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Robert Dawson ,  Mark I. Gardner ,  Frederick N. Hause ,  H. Jim Fulford, Jr. ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76895

摘要： A local interconnect (LI) structure is formed by forming a silicide layer in selected regions of a semiconductor structure then depositing an essentially uniform layer of transition or refractory metal overlying the semiconductor structure. The metal local interconnect is deposited without forming in intermediate insulating layer between the silicide and metal layers to define contact openings or vias. In some embodiments, titanium a suitable metal for formation of the local interconnect. Suitable selected regions for silicide layer formation include, for example, silicided source/drain (S/D) regions and silicided gate contact regions. The silicided regions form uniform structures for electrical coupling to underlying doped regions that are parts of one or more semiconductor devices. In integrated circuits in which an etchstop layer is desired for the patterning of the metal film, a first optional insulating layer is deposited prior to deposition of the metal film. In one example, the insulating layer is a silicon dioxide (oxide) layer that is typically less than 10 nm in thickness.

摘要翻译： 通过在半导体结构的选定区域中形成硅化物层然后沉积覆盖在半导体结构上的基本均匀的过渡或难熔金属层来形成局部互连（LI）结构。 在硅化物和金属层之间的中间绝缘层中沉积金属局部互连以限定接触开口或通孔。 在一些实施例中，钛是用于形成局部互连的合适金属。 用于硅化物层形成的合适的选定区域包括例如硅化源极/漏极（S / D）区域和硅化物栅极接触区域。 硅化区域形成均匀的结构，用于电耦合到作为一个或多个半导体器件的部分的下掺杂区域。 在需要蚀刻阻挡层用于图案化金属膜的集成电路中，在沉积金属膜之前沉积第一可选绝缘层。 在一个示例中，绝缘层是通常小于10nm厚度的二氧化硅（氧化物）层。

公开(公告)号：US6087706A

公开(公告)日：2000-07-11

申请号：US56834

申请日：1998-04-07

申请人： Robert Dawson ,  Mark I. Gardner ,  Frederick N. Hause ,  H. Jim Fulford, Jr. ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Robert Dawson ,  Mark I. Gardner ,  Frederick N. Hause ,  H. Jim Fulford, Jr. ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L21/265 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/78 ,  H01L29/00 ,  H01L29/94

CPC分类号： H01L21/26586 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/41766 ,  H01L29/66636 ,  H01L29/7833

摘要： A semiconductor integrated circuit with a transistor formed within an active area defined by side-walls of a shallow trench isolation region, and method of fabrication thereof, is described. A gate electrode is formed over a portion of the active area and LDD regions formed that are self-aligned to both the gate electrode and the trench side-walls. A dielectric spacer is formed adjacent the gate electrode and extending to the trench side-walls. In this manner, the spacers essentially cover the LDD regions. Source and drain regions are formed that are adjacent the trench side-walls wherein the spacer serves to protect at least a portion of the LDD regions to maintain a spacing of the S/D regions from the gate electrode edge. In this manner an advantageously lowered E.sub.M provided by LDD regions is maintained. In some embodiments of the present invention, S/D regions are formed by implantation through the trench side-walls.

摘要翻译： 描述了一种形成在由浅沟槽隔离区域的侧壁限定的有源区域内的晶体管的半导体集成电路及其制造方法。 在有源区域的一部分上形成栅电极，形成与栅极电极和沟槽侧壁自对准的LDD区域。 形成在栅电极附近并延伸到沟槽侧壁的电介质垫片。 以这种方式，间隔件基本上覆盖LDD区域。 形成与沟槽侧壁相邻的源极区和漏极区，其中间隔物用于保护LDD区的至少一部分以保持S / D区与栅电极边缘的间隔。 以这种方式，维持由LDD区域提供的有利的降低的EM。 在本发明的一些实施例中，通过在沟槽侧壁上注入形成S / D区域。

公开(公告)号：US5885887A

公开(公告)日：1999-03-23

申请号：US847752

申请日：1997-04-21

申请人： Frederick N. Hause ,  Robert Dawson ,  H. Jim Fulford Jr. ,  Mark I. Gardner ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Frederick N. Hause ,  Robert Dawson ,  H. Jim Fulford Jr. ,  Mark I. Gardner ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/423 ,  H01L21/38

CPC分类号： H01L29/6659 ,  H01L21/28114 ,  H01L21/823842 ,  H01L29/42376

摘要： A method of making an IGFET with a selectively doped multilevel polysilicon gate that includes upper and lower polysilicon gate levels is disclosed. The method includes providing a semiconductor substrate with an active region, forming a gate insulator on the active region, forming a a lower polysilicon layer on the gate insulator, forming a first masking layer over the lower polysilicon layer, etching the lower polysilicon layer through openings in the first masking layer using the first masking layer as an etch mask for a portion of the lower polysilicon layer that forms the lower polysilicon gate level over the active region, removing the first masking layer, forming the upper polysilicon gate level on the lower polysilicon gate level after removing the first masking layer, introducing a dopant into the upper polysilicon gate level without introducing the dopant into the substrate, diffusing the dopant from the upper polysilicon gate level into the lower polysilicon gate level, and forming a source and drain in the active region. Advantageously, the lower polysilicon gate level has both an accurately defined length to provide the desired channel length and a well-controlled doping concentration to provide the desired threshold voltage.

摘要翻译： 公开了一种制造具有选择性掺杂多电平多晶硅栅极的IGFET的方法，其包括上和下多晶硅栅极电平。 该方法包括提供具有有源区的半导体衬底，在有源区上形成栅极绝缘体，在栅极绝缘体上形成下部多晶硅层，在下部多晶硅层上形成第一掩蔽层，通过下部多晶硅层的开口蚀刻下部多晶硅层 所述第一掩模层使用所述第一掩模层作为用于在所述有源区上形成所述下多晶硅栅极电平的所述下多晶硅层的一部分的蚀刻掩模，去除所述第一掩模层，在所述下多晶硅栅极上形成所述上多晶硅栅极电平 在去除第一掩模层之后，将掺杂剂引入上多晶硅栅极级，而不将掺杂剂引入衬底中，将掺杂剂从上多晶硅栅极级扩散到下多晶硅栅极电平，并在活性层中形成源极和漏极 地区。 有利地，下多晶硅栅极电平具有精确限定的长度以提供期望的沟道长度和良好控制的掺杂浓度以提供期望的阈值电压。

公开(公告)号：US5877050A

公开(公告)日：1999-03-02

申请号：US711956

申请日：1996-09-03

申请人： Mark I. Gardner ,  Derick J. Wristers ,  H. Jim Fulford, Jr.

发明人： Mark I. Gardner ,  Derick J. Wristers ,  H. Jim Fulford, Jr.

IPC分类号： H01L21/8238

CPC分类号： H01L21/823814

摘要： A method of making N-channel and P-channel IGFETs is disclosed. The method includes, in sequence, the steps of partially doping a first source and a first drain in a first active region of a semiconductor substrate, applying a first tube anneal while a second active region of the semiconductor substrate is devoid of source/drain doping, partially doping a second source and a second drain in the second active region, applying a second tube anneal, fully doping the first source and the first drain, applying a first rapid thermal anneal, fully doping the second source and the second drain, and applying a second rapid thermal anneal. Advantageously, the first and second tube anneals provide control over the channel junction locations, and the first and second rapid thermal anneals provide rapid drive-in for subsequent source/drain doping spaced from the channel junctions.

摘要翻译： 公开了制造N沟道和P沟道IGFET的方法。 该方法依次包括在半导体衬底的第一有源区域中部分地掺杂第一源极和第一漏极的步骤，施加第一管退火，而半导体衬​​底的第二有源区域没有源极/漏极掺杂 在第二有源区中部分地掺杂第二源极和第二漏极，施加第二管退火，完全掺杂第一源极和第一漏极，施加第一快速热退火，完全掺杂第二源极和第二漏极，以及 应用第二快速热退火。 有利地，第一和第二管退火提供对通道结位置的控制，并且第一和第二快速热退火为与通道结隔开的后续源极/漏极掺杂提供快速驱动。

公开(公告)号：US5869879A

公开(公告)日：1999-02-09

申请号：US761399

申请日：1996-12-06

申请人： H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Derick J. Wristers

发明人： H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Derick J. Wristers

IPC分类号： H01L21/8238 ,  H01L29/78 ,  H01L29/00

CPC分类号： H01L29/7833 ,  H01L21/823814 ,  Y10S257/90

摘要： An integrated circuit is formed whereby junction of NMOS transistors are formed dissimilar to junctions of PMOS transistors. The NMOS transistors include an LDD area, an MDD area and a heavy concentration source/drain area. Conversely, the PMOS transistor include an LDD area and a source/drain area. The NMOS transistor junction is formed dissimilar from the PMOS transistor junction to take into account the less mobile nature of the junction dopants relative to the PMOS dopants. Thus, a lessening of the LDD area and the inclusion of an MDD area provide lower source/drain resistance and higher ohmic connectivity in the NMOS device. The PMOS junction includes a relatively large LDD area so as to draw the highly mobile, heavy concentration boron atoms away from the PMOS channel.