公开(公告)号：US06552776B1

公开(公告)日：2003-04-22

申请号：US09183176

申请日：1998-10-30

申请人： Derick J. Wristers ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Frederick N. Hause ,  Bradley T. Moore ,  Mark W. Michael

发明人： Derick J. Wristers ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Frederick N. Hause ,  Bradley T. Moore ,  Mark W. Michael

IPC分类号： G03B2754

CPC分类号： G03F7/70558 ,  G03F7/70191 ,  G03F7/706

摘要： A photolithographic system including a light filter that varies light intensity according to measured dimensional data that characterizes a lens error is disclosed. The light filter compensates for the lens error by reducing the light intensity of the image pattern as the lens error increases. In this manner, when the lens error causes focusing variations that result in enlarged portions of the image pattern, the light filter reduces the light intensity transmitted to the enlarged portions of the image pattern. This, in turn, reduces the rate in which regions of the photoresist layer beneath the enlarged portions of the image pattern are rendered soluble to a subsequent developer. As a result, after the photoresist layer is developed, linewidth variations that otherwise result from the lens error are reduced due to the light filter. Preferably, the light filter includes a light-absorbing film such as a semi-transparent layer such as calcium fluoride on a light-transmitting base such as a quartz plate, and the thickness of the light-absorbing film varies in accordance with the measured dimensional data to provide the desired variations in light intensity. The invention is particularly well-suited for patterning a photoresist layer that defines polysilicon gates of an integrated circuit device.

摘要翻译： 公开了一种光刻系统，其包括根据测量的尺寸数据来表征透镜误差来改变光强度的滤光器。 光滤波器通过降低镜头误差增大时图像图案的光强度来补偿镜头误差。 以这种方式，当透镜错误导致导致图像图案的放大部分的聚焦变化时，光过滤器降低传输到图像图案的扩大部分的光强度。 这又降低了图像图案的放大部分之下的光致抗蚀剂层的区域变得可溶于后续显影剂的速率。 结果，在光致抗蚀剂层显影之后，由于滤光器而导致透镜误差导致的线宽变化会降低。 优选地，光滤波器包括诸如石英板等透光基底上的诸如氟化钙的半透明层的光吸收膜，并且光吸收膜的厚度根据测量的尺寸而变化 数据以提供所需的光强度变化。 本发明特别适用于图案化限定集成电路器件的多晶硅栅极的光致抗蚀剂层。

公开(公告)号：US6060345A

公开(公告)日：2000-05-09

申请号：US844924

申请日：1997-04-21

申请人： Frederick N. Hause ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Frederick N. Hause ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L21/8238 ,  H01L27/092

CPC分类号： H01L21/823814

摘要： A method of making NMOS and PMOS devices with reduced masking steps is disclosed. The method includes providing a semiconductor substrate with a first active region of first conductivity type and a second active region of second conductivity type, forming a gate material over the first and second active regions, forming a first masking layer over the gate material, etching the gate material using the first masking layer as an etch mask to form a first gate over the first active region and a second gate over the second active region, implanting a dopant of second conductivity type into the first and second active regions using the first masking layer as an implant mask, forming a second masking layer that covers the first active region and includes an opening above the second active region, and implanting a dopant of first conductivity type into the second active region using the first and second masking layers as an implant mask. Advantageously, the dopant of first conductivity type counterdopes the dopant of second conductivity type in the second active region, thereby providing source and drain regions of second conductivity type in the first active region and source and drain regions of first conductivity type in the second active region with a single masking step and without subjecting either gate to dopants of first and second conductivity type.

摘要翻译： 公开了一种制造具有减小的掩蔽步骤的NMOS和PMOS器件的方法。 该方法包括提供具有第一导电类型的第一有源区和第二导电类型的第二有源区的半导体衬底，在第一和第二有源区上形成栅极材料，在栅极材料上形成第一掩模层， 栅极材料，使用第一掩模层作为蚀刻掩模，以在第一有源区上形成第一栅极，在第二有源区上形成第二栅极，使用第一掩模层将第二导电类型的掺杂剂注入到第一和第二有源区中 作为注入掩模，形成覆盖第一有源区并且包括在第二有源区上方的开口的第二掩模层，以及使用第一和第二掩模层作为注入掩模将第一导电类型的掺杂剂注入到第二有源区中 。 有利地，第一导电类型的掺杂剂在第二有源区域中抵消第二导电类型的掺杂剂，从而在第一有源区域中提供第二导电类型的源极和漏极区域，并且在第二有源区域中提供第一导电类型的源极和漏极区域 具有单个掩蔽步骤，并且不对任一个栅极施加第一和第二导电类型的掺杂剂。

公开(公告)号：US5962894A

公开(公告)日：1999-10-05

申请号：US30052

申请日：1998-02-24

申请人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L21/336 ,  H01L29/417 ,  H01L29/423 ,  H01L29/76 ,  H01L31/062

CPC分类号： H01L29/41775 ,  H01L29/66621 ,  H01L29/78

摘要： An IGFET with a gate electrode and metal spacers in a trench is disclosed. The IGFET includes a trench with opposing sidewalls and a bottom surface in a semiconductor substrate, metal spacers adjacent to the sidewalls and the bottom surface, a gate insulator on the bottom surface between the metal spacers, protective insulators on the metal spacers, a gate electrode on the gate insulator and protective insulators, and a source and drain adjacent to the bottom surface. A method of forming the IGFET includes implanting a doped layer into the substrate, etching completely through the doped layer and partially through the substrate to form the trench and split the doped layer into source and drain regions, applying a high-temperature anneal to diffuse the source and drain regions beneath the bottom surface, depositing a blanket layer of conductive metal over the substrate and applying an anisotropic etch to form the metal spacers, depositing a continuous insulative layer over the substrate to provide the gate insulator and the protective insulators, depositing a blanket layer of gate electrode material over the substrate, and polishing the gate electrode material so that the gate electrode is substantially aligned with a top surface of the substrate. Advantageously, the channel length is significantly smaller than the trench length, and the metal spacers reduce the parasitic resistance of lightly doped source and drain regions.

摘要翻译： 公开了具有沟槽中的栅电极和金属间隔物的IGFET。 IGFET包括具有相对的侧壁和半导体衬底中的底表面的沟槽，与侧壁和底表面相邻的金属间隔物，位于金属间隔物之间​​的底表面上的栅极绝缘体，金属间隔物上的保护绝缘体，栅电极 在栅极绝缘体和保护绝缘体上，以及与底表面相邻的源极和漏极。 形成IGFET的方法包括将掺杂层注入到衬底中，完全通过掺杂层蚀刻并部分地穿过衬底以形成沟槽并将掺杂层分裂成源极和漏极区域，施加高温退火以扩散 在底表面下方的源极和漏极区域，在衬底上沉积导电金属的覆盖层，并施加各向异性蚀刻以形成金属间隔物，在衬底上沉积连续的绝缘层以提供栅极绝缘体和保护绝缘体， 覆盖衬底上的栅电极材料层，并且对栅电极材料进行抛光，使得栅电极基本上与衬底的顶表面对准。 有利地，沟道长度显着小于沟槽长度，并且金属间隔物减少了轻掺杂源极和漏极区域的寄生电阻。

公开(公告)号：US5930634A

公开(公告)日：1999-07-27

申请号：US844927

申请日：1997-04-21

申请人： Frederick N. Hause ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Frederick N. Hause ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/66575 ,  H01L21/28035 ,  H01L21/28052 ,  H01L29/42376 ,  H01L29/4925 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of making an IGFET with a multilevel gate that includes upper and lower gate levels is disclosed. The method includes providing a semiconductor substrate with an active region, forming a gate insulator on the active region, forming a first gate material with a thickness of at most 1000 angstroms on the gate inslator and over the active region, forming a first photoresist layer over the first gate material, irradiating the first photoresist layer with a first image pattern and removing irradiated portions of the first photoresist layer to provide openings above the active region, etching the first gate material through the openings in the first photoresist layer using the first photoresist layer as an etch mask for a portion of the first gate material that forms a lower gate level, removing the first photoresist layer, forming an upper gate level on the lower gate level after removing the first photoresist layer, and forming a source and drain in the active region. Advantageously, the first photoresist layer can be ultra-thin to enhance the accuracy in which the image pattern is replicated, thereby reducing variations in channel length and device performance.

摘要翻译： 公开了一种制造具有包括上下栅极电平的多电平栅极的IGFET的方法。 该方法包括提供具有有源区的半导体衬底，在有源区上形成栅极绝缘体，在栅极绝缘体上并在有源区上形成厚度至多为1000埃的第一栅极材料，形成第一光致抗蚀剂层 第一栅极材料，用第一图案图案照射第一光致抗蚀剂层，并去除第一光致抗蚀剂层的照射部分以在有源区上方提供开口，使用第一光致抗蚀剂层蚀刻通过第一光致抗蚀剂层中的开口的第一栅极材料 作为用于形成下栅极电平的第一栅极材料的一部分的蚀刻掩模，去除第一光致抗蚀剂层，在去除第一光致抗蚀剂层之后在下栅极电平上形成上栅极电平，并在其中形成源极和漏极 活跃区域。 有利地，第一光致抗蚀剂层可以是超薄的，以提高复制图像图案的精度，从而减少通道长度和器件性能的变化。

公开(公告)号：US5877058A

公开(公告)日：1999-03-02

申请号：US703272

申请日：1996-08-26

申请人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L21/336 ,  H01L21/3205

CPC分类号： H01L29/6659 ,  H01L29/6656

摘要： An IGFET with metal spacers is disclosed. The IGFET includes a gate electrode on a gate insulator on a semiconductor substrate. Sidewall insulators are adjacent to opposing vertical edges of the gate electrode, and metal spacers are formed on the substrate and adjacent to the sidewall insulators. The metal spacers are electrically isolated from the gate electrode but contact portions of the drain and the source. Preferably, the metal spacers are adjacent to edges of the gate insulator beneath the sidewall insulators. The metal spacers are formed by depositing a metal layer over the substrate then applying an anisotropic etch. In one embodiment, the metal spacers contact lightly and heavily doped drain and source regions, thereby increasing the conductivity between the heavily doped drain and source regions and the channel underlying the gate electrode. The metal spacers can also provide low resistance drain and source contacts.

摘要翻译： 公开了具有金属间隔物的IGFET。 IGFET在半导体衬底上的栅极绝缘体上包括栅电极。 侧壁绝缘体与栅电极的相对的垂直边缘相邻，并且金属间隔件形成在衬底上并且与侧壁绝缘体相邻。 金属间隔物与栅电极电绝缘，但是漏极和源极的接触部分。 优选地，金属间隔件邻近侧壁绝缘体之下的栅极绝缘体的边缘。 通过在衬底上沉积金属层然后施加各向异性蚀刻来形成金属间隔物。 在一个实施例中，金属间隔物接触轻掺杂和重掺杂的漏极和源极区域，从而增加重掺杂漏极和源极区域之间的导电性以及栅电极下面的沟道。 金属间隔物还可以提供低电阻漏极和源极触点。

公开(公告)号：US5710054A

公开(公告)日：1998-01-20

申请号：US703273

申请日：1996-08-26

申请人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L21/225 ,  H01L21/28 ,  H01L21/336 ,  H01L29/08 ,  H01L29/78 ,  H01L21/265 ,  H01L21/385

CPC分类号： H01L29/66575 ,  H01L21/2256 ,  H01L21/2257 ,  H01L21/28105 ,  H01L21/28114 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

摘要： A method of forming a shallow junction in an IGFET is disclosed. The method includes forming a gate insulator on a semiconductor substrate of first conductivity type, forming a gate electrode on the gate insulator, forming a sidewall insulator on an edge of the gate electrode, forming a silicon-based spacer over the substrate such that the sidewall insulator separates and electrically isolates the spacer and the gate electrode, and diffusing a dopant of second conductivity type from the spacer into the substrate. The diffused dopant forms a shallow region of second conductivity type in the substrate, and a shallow junction is substantially laterally aligned with the edge of the gate electrode.

摘要翻译： 公开了一种在IGFET中形成浅结的方法。 该方法包括在第一导电类型的半导体衬底上形成栅极绝缘体，在栅极绝缘体上形成栅电极，在栅电极的边缘上形成侧壁绝缘体，在衬底上形成硅基间隔物，使得侧壁 绝缘体分离并电隔离间隔物和栅电极，并将第二导电类型的掺杂剂从间隔物扩散到衬底中。 扩散掺杂剂在衬底中形成第二导电类型的浅区域，并且浅结与栅电极的边缘基本上横向对齐。

公开(公告)号：US06188114B1

公开(公告)日：2001-02-13

申请号：US09204016

申请日：1998-12-01

申请人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L31119

CPC分类号： H01L29/41783 ,  H01L29/41775 ,  H01L29/66575 ,  H01L29/6659

摘要： An IGFET with metal spacers is disclosed. The IGFET includes a gate electrode on a gate insulator on a semiconductor substrate. Sidewall insulators are adjacent to opposing vertical edges of the gate electrode, and metal spacers are formed on the substrate and adjacent to the sidewall insulators. The metal spacers are electrically isolated from the gate electrode but contact portions of the drain and the source. Preferably, the metal spacers are adjacent to edges of the gate insulator beneath the sidewall insulators. The metal spacers are formed by depositing a metal layer over the substrate then applying an anisotropic etch. In one embodiment, the metal spacers contact lightly and heavily doped drain and source regions, thereby increasing the conductivity between the heavily doped drain and source regions and the channel underlying the gate electrode. The metal spacers can also provide low resistance drain and source contacts.

摘要翻译： 公开了具有金属间隔物的IGFET。 IGFET在半导体衬底上的栅极绝缘体上包括栅电极。 侧壁绝缘体与栅电极的相对的垂直边缘相邻，并且金属间隔件形成在衬底上并且与侧壁绝缘体相邻。 金属间隔物与栅电极电绝缘，但是漏极和源极的接触部分。 优选地，金属间隔件邻近侧壁绝缘体之下的栅极绝缘体的边缘。 通过在衬底上沉积金属层然后施加各向异性蚀刻来形成金属间隔物。 在一个实施例中，金属间隔物接触轻掺杂和重掺杂的漏极和源极区域，从而增加重掺杂漏极和源极区域之间的导电性以及栅电极下面的沟道。 金属间隔物还可以提供低电阻漏极和源极触点。

公开(公告)号：US6166354A

公开(公告)日：2000-12-26

申请号：US876381

申请日：1997-06-16

申请人： Frederick N. Hause ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Frederick N. Hause ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： C30B31/12 ,  C30B31/18 ,  F27B5/14

CPC分类号： C30B31/18 ,  C30B31/12

摘要： An optical monitoring of electrical characteristics of devices in a semiconductor is performed during an anneal step to detect the time annealing is complete and activation occurs. A surface photovoltage measurement is made during annealing to monitor the charge state on the surface of a substrate wafer to determine when the substrate is fully annealed. The surface photovoltage measurement is monitored, the time of annealing is detected, and a selected over-anneal is controlled. The surface photovoltage (SPV) measurement is performed to determine a point at which a dopant or impurity such as boron or phosphorus is annealed in a silicon lattice. In some embodiments, the point of detection is used as a feedback signal in an RTA annealing system to adjust a bank of annealing lamps for annealing and activation uniformity control. The point of detection is also used to terminate the annealing process to minimize D.sub.t.

摘要翻译： 在退火步骤期间执行半导体器件的电特性的光学监测，以检测时间退火完成并发生激活。 在退火期间进行表面光电压测量以监测衬底晶片的表面上的电荷状态，以确定衬底何时完全退火。 监测表面光电压测量，检测退火时间，并控制所选择的过退火。 执行表面光电压（SPV）测量以确定在硅晶格中退火掺杂剂或杂质如硼或磷的点。 在一些实施例中，将检测点用作RTA退火系统中的反馈信号，以调整用于退火和激活均匀性控制的退火灯组。 检测点也用于终止退火过程以最小化Dt。

公开(公告)号：US6146978A

公开(公告)日：2000-11-14

申请号：US73639

申请日：1998-05-06

申请人： Mark W. Michael ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Frederick N. Hause ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Mark W. Michael ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Frederick N. Hause ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L21/768 ,  H01L21/8238 ,  H01L21/44 ,  H01L21/4763 ,  H01L31/119

CPC分类号： H01L21/823871 ,  H01L21/76802 ,  H01L21/76895

摘要： An interlevel interconnect is formed in a window opened through an isolation layer and through an etch barrier to expose an electrode surface and an adjacent isolation barrier. The interlevel interconnect may be disposed on substantially all of a portion of the underlying electrode such as an insulated gate field effect transistor (IGFET) source/drain region surface. The etch barrier provides controlled etching to allow for overlap of the interlevel interconnect onto the isolation barrier without increased parasitic capacitance relative to conventional contact misalignments. Furthermore, allaying concerns of overlapping allows for increased utilization of source/drain region surface area by the interlevel interconnect. Furthermore, the etch barrier allows the interlevel interconnect to strap electrodes of a plurality of circuit devices while exhibiting nominal if any substrate to interlevel interconnect leakage currents.

摘要翻译： 在通过隔离层打开的窗口中并通过蚀刻屏障形成层间互连，以露出电极表面和相邻隔离屏障。 层间互连可以布置在底层电极的基本上全部的一部分上，例如绝缘栅场效应晶体管（IGFET）源/漏区表面。 蚀刻屏障提供受控的蚀刻，以允许层间互连重叠在隔离屏障上，而不增加寄生电容，相对于传统的接触不对准。 此外，消除重叠的关注允许通过层间互连增加源/漏区表面积的利用。 此外，蚀刻屏障允许层间互连以多个电路器件的带状电极同时显示标称的任何衬底以互连互连漏电流。

公开(公告)号：US6096639A

公开(公告)日：2000-08-01

申请号：US056835

申请日：1998-04-07

申请人： Robert Dawson ,  Mark I. Gardner ,  Frederick N. Hause ,  H. Jim Fulford, Jr. ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Robert Dawson ,  Mark I. Gardner ,  Frederick N. Hause ,  H. Jim Fulford, Jr. ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76895

摘要： A local interconnect (LI) structure is formed by forming a silicide layer in selected regions of a semiconductor structure then depositing an essentially uniform layer of transition or refractory metal overlying the semiconductor structure. The metal local interconnect is deposited without forming in intermediate insulating layer between the silicide and metal layers to define contact openings or vias. In some embodiments, titanium a suitable metal for formation of the local interconnect. Suitable selected regions for silicide layer formation include, for example, silicided source/drain (S/D) regions and silicided gate contact regions. The silicided regions form uniform structures for electrical coupling to underlying doped regions that are parts of one or more semiconductor devices. In integrated circuits in which an etchstop layer is desired for the patterning of the metal film, a first optional insulating layer is deposited prior to deposition of the metal film. In one example, the insulating layer is a silicon dioxide (oxide) layer that is typically less than 10 nm in thickness.

摘要翻译： 通过在半导体结构的选定区域中形成硅化物层然后沉积覆盖在半导体结构上的基本均匀的过渡或难熔金属层来形成局部互连（LI）结构。 在硅化物和金属层之间的中间绝缘层中沉积金属局部互连以限定接触开口或通孔。 在一些实施例中，钛是用于形成局部互连的合适金属。 用于硅化物层形成的合适的选定区域包括例如硅化源极/漏极（S / D）区域和硅化物栅极接触区域。 硅化区域形成均匀的结构，用于电耦合到作为一个或多个半导体器件的部分的下掺杂区域。 在需要蚀刻阻挡层用于图案化金属膜的集成电路中，在沉积金属膜之前沉积第一可选绝缘层。 在一个示例中，绝缘层是通常小于10nm厚度的二氧化硅（氧化物）层。