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公开(公告)号：US07730279B2
公开(公告)日：2010-06-01
申请号：US12429676
申请日：2009-04-24
申请人： Adam P. Burns , Michael N. Day , Brian Flachs , H. Peter Hofstee , Charles R. Johns , John Liberty
发明人： Adam P. Burns , Michael N. Day , Brian Flachs , H. Peter Hofstee , Charles R. Johns , John Liberty
IPC分类号： G06F12/00
CPC分类号： G06F12/0661 , G06F12/0223
摘要： A system for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control processor in the multiprocessor system or the associated processor itself. The operating system sets the value stored in the local storage limit register when the operating system initializes a context switch in the processor. When the processor accesses the local storage using a request address, the local storage address corresponding to the request address is compared against the local storage limit size value in order to determine if the local storage address, or a modulo of the local storage address, is used to access the local storage.
摘要翻译： 提供了用于限制处理器的本地存储器的大小的系统。 与用于设置本地存储大小限制的处理器相关联地提供设施。 该设施是一种特权设施，只能由在多处理器系统或相关处理器本身的控制处理器上运行的操作系统访问。 当操作系统初始化处理器中的上下文切换时，操作系统设置存储在本地存储限制寄存器中的值。 当处理器使用请求地址访问本地存储器时，将与请求地址相对应的本地存储地址与本地存储限制大小值进行比较，以便确定本地存储地址或本地存储地址的模数是否为 用于访问本地存储。
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公开(公告)号：US20090204781A1
公开(公告)日：2009-08-13
申请号：US12429676
申请日：2009-04-24
申请人： Adam P. Burns , Michael N. Day , Brian Flachs , H. Peter Hofstee , Charles R. Johns , John Liberty
发明人： Adam P. Burns , Michael N. Day , Brian Flachs , H. Peter Hofstee , Charles R. Johns , John Liberty
CPC分类号： G06F12/0661 , G06F12/0223
摘要： A system for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control processor in the multiprocessor system or the associated processor itself. The operating system sets the value stored in the local storage limit register when the operating system initializes a context switch in the processor. When the processor accesses the local storage using a request address, the local storage address corresponding to the request address is compared against the local storage limit size value in order to determine if the local storage address, or a modulo of the local storage address, is used to access the local storage.
摘要翻译： 提供了用于限制处理器的本地存储器的大小的系统。 与用于设置本地存储大小限制的处理器相关联地提供设施。 该设施是一种特权设施，只能由在多处理器系统或相关处理器本身的控制处理器上运行的操作系统访问。 当操作系统初始化处理器中的上下文切换时，操作系统设置存储在本地存储限制寄存器中的值。 当处理器使用请求地址访问本地存储器时，将与请求地址相对应的本地存储地址与本地存储限制大小值进行比较，以便确定本地存储地址或本地存储地址的模数是否为 用于访问本地存储。
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公开(公告)号：US07533238B2
公开(公告)日：2009-05-12
申请号：US11208376
申请日：2005-08-19
申请人： Adam P. Burns , Michael N. Day , Brian Flachs , H. Peter Hofstee , Charles R. Johns , John Liberty
发明人： Adam P. Burns , Michael N. Day , Brian Flachs , H. Peter Hofstee , Charles R. Johns , John Liberty
IPC分类号： G06F12/00
CPC分类号： G06F12/0661 , G06F12/0223
摘要： A method for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control processor in the multiprocessor system or the associated processor itself The operating system sets the value stored in the local storage limit register when the operating system initializes a context switch in the processor. When the processor accesses the local storage using a request address, the local storage address corresponding to the request address is compared against the 1ocal storage limit size value in order to determine if the local storage address, or a modulo of the local storage address, is used to access the local storage.
摘要翻译： 提供了一种用于限制处理器的本地存储器的大小的方法。 与用于设置本地存储大小限制的处理器相关联地提供设施。 该设施是一个特权设施，只能由在多处理器系统或相关处理器本身的控制处理器上运行的操作系统访问。当操作系统初始化上下文切换时，操作系统设置存储在本地存储限制寄存器中的值 在处理器中。 当处理器使用请求地址访问本地存储器时，将与请求地址相对应的本地存储地址与本地存储限制大小值进行比较，以便确定本地存储地址或本地存储地址的模数是否为 用于访问本地存储。
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公开(公告)号：US20120110348A1
公开(公告)日：2012-05-03
申请号：US12917092
申请日：2010-11-01
申请人： H. Peter Hofstee , Brian Flachs , Charles R. Johns
发明人： H. Peter Hofstee , Brian Flachs , Charles R. Johns
CPC分类号： G06F12/1009 , G06F12/1408
摘要： A system comprises a memory module configured to store signed page table data and a selected processing element coupled to the memory module. The selected processing element is one of a plurality of processing elements, which together comprise a portion of a multiprocessor system. The selected processing element is configured to authenticate page table management code and, based on authenticated page table management code, to sign page table data that is subsequently stored in the memory module, and to verify signed page table data that is read from the memory module.
摘要翻译： 系统包括被配置为存储经签名的页表数据的存储器模块和耦合到存储器模块的所选择的处理元件。 所选择的处理元件是多个处理元件之一，它们一起构成多处理器系统的一部分。 所选择的处理元件被配置为认证页表管理代码，并且基于经认证的页表管理代码来签名随后存储在存储器模块中的页表数据，并且验证从存储器模块读取的经签名页表数据 。
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5.发明申请Design Structure For A Processor System With Background Error Handling Feature 审中-公开具有背景错误处理功能的处理器系统的设计结构公开(公告)号：US20090070654A1
公开(公告)日：2009-03-12
申请号：US12272812
申请日：2008-11-18
CPC分类号： H03M13/19 , G06F11/1044 , H03M13/09
摘要： A design structure for a processor system may be embodied in a machine readable medium for designing, manufacturing or testing a processor integrated circuit. The design structure may embody a processor system that integrates error correcting code (ECC) detection and correction hardware within an memory management circuit. The design structure may specify ECC hardware circuitry that provides detection, correction and generation of ECC data bits in conjunction with memory data read and writes. The design structure for the processor system may permit the detection and correction of soft single bit errors read from local memory in-line while using read modify write DMA circuit logic to correct local memory data. The design structure may provide for local memory data error detection and correction in a background memory scrub process without the need for additional in-line data logic.
摘要翻译： 用于处理器系统的设计结构可以体现在用于设计，制造或测试处理器集成电路的机器可读介质中。 该设计结构可以包括在存储器管理电路内集成纠错码（ECC）检测和校正硬件的处理器系统。 设计结构可以指定ECC硬件电路，其提供与存储器数据读取和写入相结合的ECC数据位的检测，校正和生成。 处理器系统的设计结构可以允许检测和校正从本地存储器在线读取的软单位错误，同时使用读修改写DMA电路逻辑来校正本地存储器数据。 设计结构可以在后台存储器擦除过程中提供本地存储器数据错误检测和校正，而不需要附加的在线数据逻辑。
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公开(公告)号：US20120254603A1
公开(公告)日：2012-10-04
申请号：US13074438
申请日：2011-03-29
IPC分类号： G06F1/24
CPC分类号： G06F9/5066
摘要： Mechanisms are provided for performing approximate run-ahead computations. A first group of compute engines is selected to execute full computations on a full set of input data. A second group of compute engines is selected to execute computations on a sampled subset of the input data. A third group of compute engines is selected to compute a difference in computation results between first computation results generated by the first group of compute engines and second computation results generated by the second group of compute engines. The second group of compute engines is reconfigured based on the difference generated by the third group of compute engines.
摘要翻译： 提供了执行近似预测计算的机制。 选择第一组计算引擎以对完整的输入数据集执行完全计算。 选择第二组计算引擎来对输入数据的采样子集执行计算。 选择第三组计算引擎以计算由第一组计算引擎生成的第一计算结果与由第二组计算引擎生成的第二计算结果之间的计算结果的差异。 基于由第三组计算引擎产生的差异来重新配置第二组计算引擎。
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公开(公告)号：US08510546B2
公开(公告)日：2013-08-13
申请号：US13074438
申请日：2011-03-29
CPC分类号： G06F9/5066
摘要： Mechanisms are provided for performing approximate run-ahead computations. A first group of compute engines is selected to execute full computations on a full set of input data. A second group of compute engines is selected to execute computations on a sampled subset of the input data. A third group of compute engines is selected to compute a difference in computation results between first computation results generated by the first group of compute engines and second computation results generated by the second group of compute engines. The second group of compute engines is reconfigured based on the difference generated by the third group of compute engines.
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公开(公告)号：US20120254604A1
公开(公告)日：2012-10-04
申请号：US13468064
申请日：2012-05-10
IPC分类号： G06F9/06
CPC分类号： G06F9/5066
摘要： Mechanisms are provided for performing approximate run-ahead computations. A first group of compute engines is selected to execute full computations on a full set of input data. A second group of compute engines is selected to execute computations on a sampled subset of the input data. A third group of compute engines is selected to compute a difference in computation results between first computation results generated by the first group of compute engines and second computation results generated by the second group of compute engines. The second group of compute engines is reconfigured based on the difference generated by the third group of compute engines.
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9.发明申请Apparatus for Improving Single Thread Performance through Speculative Processing 审中-公开通过投机处理提高单线性能的装置公开(公告)号：US20080201563A1
公开(公告)日：2008-08-21
申请号：US12110400
申请日：2008-04-28
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3824 , G06F9/3851 , G06F9/3863 , G06F9/461
摘要： An apparatus is provided for using multiple thread contexts to improve processing performance of a single thread. When an exceptional instruction is encountered, the exceptional instruction and any predicted instructions are reloaded into a buffer of a first thread context. A state of the register file at the time of encountering the exceptional instruction is maintained in a register file of the first thread context. The instructions in the pipeline are executed speculatively using a second register file in a second thread context. During speculative execution, cache misses may cause loading of data to the cache may be performed. Results of the speculative execution are written to the second register file. When a stopping condition is met, contents of the first register file are copied to the second register file and the reloaded instructions are released to the execution pipeline.
摘要翻译： 提供了一种用于使用多个线程上下文来提高单个线程的处理性能的装置。 当遇到异常指令时，异常指令和任何预测指令被重新加载到第一个线程上下文的缓冲区中。 在遇到异常指令时，寄存器文件的状态被保存在第一个线程上下文的寄存器文件中。 使用第二线程上下文中的第二寄存器文件推测地执行流水线中的指令。 在推测执行期间，高速缓存未命中可能导致数据加载到缓存可能被执行。 推测执行的结果将写入第二个寄存器文件。 当满足停止条件时，将第一寄存器文件的内容复制到第二寄存器文件，并且重新加载的指令被释放到执行管线。
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公开(公告)号：US20120005473A1
公开(公告)日：2012-01-05
申请号：US12827726
申请日：2010-06-30
IPC分类号： G06F1/24
CPC分类号： G06F21/76 , G06F15/7867
摘要： A mechanism for securely and dynamically reconfiguring reconfigurable logic is provided. A state machine within a data processing system establishes a hardware boundary to the reconfigurable logic within the data processing system thereby forming isolated reconfigurable logic. The state machine clears any prior state existing within the isolated reconfigurable logic. The state machine authenticates a new configuration to be loaded into the isolated reconfigurable logic. The state machine determines whether the authentication of the new configuration is successful. Responsive to the authentication of the new configuration being successful, the state machine loads the new configuration into the isolated reconfigurable logic. The state machine then starts operation of the isolated reconfigurable logic.
摘要翻译： 提供了一种用于安全和动态地重新配置可重构逻辑的机制。 数据处理系统内的状态机为数据处理系统内的可重构逻辑建立硬件边界，从而形成隔离的可重配置逻辑。 状态机清除分离的可重新配置逻辑中存在的任何先前状态。 状态机验证要加载到隔离可重配置逻辑中的新配置。 状态机确定新配置的认证是否成功。 响应于新配置的认证成功，状态机将新配置加载到隔离的可重配置逻辑中。 状态机然后启动隔离的可重新配置逻辑的操作。
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