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    Mapping entry invalidation
    2.
    发明授权
    Mapping entry invalidation 有权

    公开(公告)号：US11249918B2

    公开(公告)日：2022-02-15

    申请号：US16174738

    申请日：2018-10-30

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Shawn K. Walker ,  Christopher Shawn Kroeger ,  Derek A. Sherlock

    IPC: G06F12/1009 ,  G06F13/16 ,  G06F13/42

    Abstract: A memory access system may include a first memory address translator, a second memory address translator and a mapping entry invalidator. The first memory address translator translates a first virtual address in a first protocol of a memory access request to a second virtual address in a second protocol and tracks memory access request completions. The second memory address translator is to translate the second virtual address to a physical address of a memory. The mapping entry invalidator requests invalidation of a first mapping entry of the first mapping address translator requests invalidation of a second mapping entry of the second memory address translator corresponding to the first mapping entry following invalidation of the first mapping entry and based upon the tracked memory access request completions.

    SYSTEM AND METHOD FOR TRACKING PERSISTENT FLUSHES
    3.
    发明申请
    SYSTEM AND METHOD FOR TRACKING PERSISTENT FLUSHES 有权

    公开(公告)号：US20210342266A1

    公开(公告)日：2021-11-04

    申请号：US16863977

    申请日：2020-04-30

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Derek A. Sherlock ,  Gregg B. Lesartre

    IPC: G06F12/0804

    Abstract: One embodiment can provide an apparatus. The apparatus can include a persistent flush (PF) cache and a PF-tracking logic coupled to the PF cache. The PF-tracking logic is to: in response to receiving, from a media controller, an acknowledgment to a write request, determine whether the PF cache includes an entry corresponding to the media controller; in response to the PF cache not including the entry corresponding to the media controller, allocate an entry in the PF cache for the media controller; in response to receiving a persistence checkpoint, identify a media controller from a plurality of media controllers based on entries stored in the PF cache; issue a persistent flush request to the identified media controller to persist write requests received by the identified media controller; and remove an entry corresponding to the identified media controller from the PF cache subsequent to issuing the persistent flush request.

    PCIe write request acknowledgment
    4.
    发明授权
    PCIe write request acknowledgment 有权

    公开(公告)号：US10599598B1

    公开(公告)日：2020-03-24

    申请号：US16134499

    申请日：2018-09-18

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Shawn K. Walker ,  Derek A. Sherlock ,  Gary Gostin

    IPC: G06F13/38 ,  G06F13/40 ,  G06F13/42 ,  G06F3/06 ,  H04L29/08

    Abstract: A PCIe (Peripheral Component Interconnect Express) protocol converter for connection to a central processing unit (CPU) node having a root complex, a CPU memory fabric and CPU memory may include independent PCIe links, a fabric interface and a fabric switch connected to the fabric interface. Each of the links may include an endpoint for connection to the root complex. The fabric switch is connected to the fabric interface of each of the links and is connectable to a remote node. The fabric switch transmits writes of a single write request from the remote node across both links. Each fabric interface is to transmit an acknowledgment to the remote node in response to a write of the writes becoming observable at the CPU node hi Michael, hi Michael,.

    End-to-end negative acknowledgment
    5.
    发明授权
    End-to-end negative acknowledgment 有权

    公开(公告)号：US10594442B2

    公开(公告)日：2020-03-17

    申请号：US15513891

    申请日：2014-10-24

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Derek A. Sherlock

    IPC: H04L1/16 ,  H04L1/08 ,  H04L12/709

    Abstract: A processing device includes a transceiver to be coupled to a link and control logic coupled to the transceiver. The control logic is to assign a unique sequence identifier to each packet to be transmitted across the link to a receiving node and transmit packets via the transceiver across the link to the receiving node. Each packet is to have a unique sequence identifier. The control logic also is to receive a message from the receiving node, the message containing the sequence identifier of a packet not correctly received by the receiving node. Based on the received message, the control logic is to cause an end-to-end negative acknowledgment (E2E NAK) packet to be transmitted to an originating node of the packet that was not correctly received.

    END-TO-END NEGATIVE ACKNOWLEDGMENT
    7.
    发明申请
    END-TO-END NEGATIVE ACKNOWLEDGMENT 审中-公开

    公开(公告)号：US20170302409A1

    公开(公告)日：2017-10-19

    申请号：US15513891

    申请日：2014-10-24

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Derek A. Sherlock

    IPC: H04L1/16 ,  H04L12/709 ,  H04L1/08

    CPC classification number: H04L1/1671 ,  H04L1/06 ,  H04L1/08 ,  H04L1/1607 ,  H04L1/1621 ,  H04L1/1628 ,  H04L45/245 ,  H04L2001/0096

    Abstract: A processing device includes a transceiver to be coupled to a link and control logic coupled to the transceiver. The control logic is to assign a unique sequence identifier to each packet to be transmitted across the link to a receiving node and transmit packets via the transceiver across the link to the receiving node. Each packet is to have a unique sequence identifier. The control logic also is to receive a message from the receiving node, the message containing the sequence identifier of a packet not correctly received by the receiving node. Based on the received message, the control logic is to cause an end-to-end negative acknowledgment (E2E NAK) packet to be transmitted to an originating node of the packet that was not correctly received.

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