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    DATA PROCESSING APPARATUSES AND METHODS
    5.
    发明申请
    DATA PROCESSING APPARATUSES AND METHODS 审中-公开

    公开(公告)号：US20190303249A1

    公开(公告)日：2019-10-03

    申请号：US15942925

    申请日：2018-04-02

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Dejan S. Milojicic ,  Keith Packard ,  Michael Woodacre ,  Andrew R. Wheeler

    IPC: G06F11/14

    Abstract: Example implementations relate to an apparatus to support providing a computing service to a client including transferring control between a primary data processing system and a secondary data processing system in response to an event; the primary data processing system comprising a processor and associated memory and the secondary data processing system comprising a processor and associated memory; the apparatus comprising: circuitry to identify restoration data; the restoration data comprising at least data associated with at least one predetermined type of memory operation of the memory associated with the primary data processing system, and circuitry to output any identified restoration data for storage in the memory associated with the processor of the secondary data processing system.

    Method and system for shared direct access storage
    6.
    发明授权
    Method and system for shared direct access storage 有权

    公开(公告)号：US11029847B2

    公开(公告)日：2021-06-08

    申请号：US15353413

    申请日：2016-11-16

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Kirill Malkin ,  Steve Dean ,  Michael Woodacre ,  Eng Lim Goh

    IPC: G06F3/06 ,  G06F9/50

    Abstract: In high performance computing, the potential compute power in a data center will scale to and beyond a billion-billion calculations per second (“Exascale” computing levels). Limitations caused by hierarchical memory architectures where data is temporarily stored in slower or less available memories will increasingly limit high performance computing systems from approaching their maximum potential processing capabilities. Furthermore, time spent and power consumed copying data into and out of a slower tier memory will increase costs associated with high performance computing at an accelerating rate. New technologies, such as the novel Zero Copy Architecture disclosed herein, where each compute node writes locally for performance, yet can quickly access data globally with low latency will be required. The result is the ability to perform burst buffer operations and in situ analytics, visualization and computational steering without the need for a data copy or movement.

    Workload management system and process
    7.
    发明授权
    Workload management system and process 有权

    公开(公告)号：US10521260B2

    公开(公告)日：2019-12-31

    申请号：US15650357

    申请日：2017-07-14

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Steven J. Dean ,  Michael Woodacre ,  Randal S. Passint ,  Eric C. Fromm ,  Thomas E. McGee ,  Michael E. Malewicki ,  Kirill Malkin

    IPC: G06F9/46 ,  G06F9/455 ,  G06F9/50 ,  G06Q10/06 ,  G06F9/54 ,  H04L29/08

    Abstract: A high performance computing (HPC) system has an architecture that separates data paths used by compute nodes exchanging computational data from the data paths used by compute nodes to obtain computational work units and save completed computations. The system enables an improved method of saving checkpoint data, and an improved method of using an analysis of the saved data to assign particular computational work units to particular compute nodes. The system includes a compute fabric and compute nodes that cooperatively perform a computation by mutual communication using the compute fabric. The system also includes a local data fabric that is coupled to the compute nodes, a memory, and a data node. The data node is configured to retrieve data for the computation from an external bulk data storage, and to store its work units in the memory for access by the compute nodes.

    Caching network fabric for high performance computing
    8.
    发明授权
    Caching network fabric for high performance computing 有权

    公开(公告)号：US10404800B2

    公开(公告)日：2019-09-03

    申请号：US15650296

    申请日：2017-07-14

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Michael Woodacre ,  Randal S. Passint

    IPC: G06F12/00 ,  H04L29/08 ,  G06F12/0817 ,  G06F12/0831 ,  H04L12/947 ,  H04L12/931

    Abstract: An apparatus and method exchange data between two nodes of a high performance computing (HPC) system using a data communication link. The apparatus has one or more processing cores, RDMA engines, cache coherence engines, and multiplexers. The multiplexers may be programmed by a user application, for example through an API, to selectively couple either the RDMA engines, cache coherence engines, or a mix of these to the data communication link. Bulk data transfer to the nodes of the HPC system may be performed using paged RDMA during initialization. Then, during computation proper, random access to remote data may be performed using a coherence protocol (e.g. MESI) that operates on much smaller cache lines.

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