公开(公告)号：US20240204789A1

公开(公告)日：2024-06-20

申请号：US18081490

申请日：2022-12-14

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Dacheng Zhou ,  Peter Tsugio Kurahashi ,  Ryan Barnhill ,  Michael James Marshall

IPC: H03M1/06

CPC classification number: H03M1/0607

Abstract: A frontend circuit of a time-interleaved ADC is provided. The frontend circuit can include a track-and-hold circuit to sample an analog input signal to the ADC, a sub-ADC circuit to convert the sampled analog input signal to a digital output signal, and a source-follower circuit. An input of the source-follower circuit can be coupled to an output of the track-and-hold circuit, and an output of the source-follower circuit can be coupled to an input of the sub-ADC circuit. The source-follower circuit is to provide buffering between the track-and-hold circuit and the sub-ADC circuit. The circuit further includes a common-mode-adjusting circuit to dynamically adjust common-mode settings of the time-interleaved ADC. While adjusting the common-mode settings, the common-mode-adjusting circuit can adjust, separately, an input common-mode voltage of the track-and-hold circuit and an input common-mode voltage of the sub-ADC circuit based on current Process, Voltage, and Temperature (PVT) conditions.

公开(公告)号：US12132492B2

公开(公告)日：2024-10-29

申请号：US18081490

申请日：2022-12-14

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Dacheng Zhou ,  Peter Tsugio Kurahashi ,  Ryan Barnhill ,  Michael James Marshall

IPC: H03M1/06 ,  H03M1/12 ,  H03M1/16 ,  H03M1/38

CPC classification number: H03M1/0607 ,  H03M1/1215 ,  H03M1/1245 ,  H03M1/167 ,  H03M1/38

Abstract: A frontend circuit of a time-interleaved ADC is provided. The frontend circuit can include a track-and-hold circuit to sample an analog input signal to the ADC, a sub-ADC circuit to convert the sampled analog input signal to a digital output signal, and a source-follower circuit. An input of the source-follower circuit can be coupled to an output of the track-and-hold circuit, and an output of the source-follower circuit can be coupled to an input of the sub-ADC circuit. The source-follower circuit is to provide buffering between the track-and-hold circuit and the sub-ADC circuit. The circuit further includes a common-mode-adjusting circuit to dynamically adjust common-mode settings of the time-interleaved ADC. While adjusting the common-mode settings, the common-mode-adjusting circuit can adjust, separately, an input common-mode voltage of the track-and-hold circuit and an input common-mode voltage of the sub-ADC circuit based on current Process, Voltage, and Temperature (PVT) conditions.

公开(公告)号：US20240255983A1

公开(公告)日：2024-08-01

申请号：US18161927

申请日：2023-01-31

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Dacheng Zhou ,  Peter Tsugio Kurahashi

IPC: G06F1/12 ,  G06F1/08

CPC classification number: G06F1/12 ,  G06F1/08

Abstract: A TI-ADC circuit and method therefor include the use of first and second level clock generators configured to receive an asynchronous reference clock signal and generate a plurality of first and second clock signals, the second level clock generator including a plurality of clock dividers connected in series, respective ones of the plurality of clock dividers being configured to divide an input clock signal in accordance with a synchronization signal; a plurality of T/H circuits respectively configured to operate in accordance with one of the first clock signals; a plurality of sub-ADCs respectively configured to operate in accordance with one of the second clock signals, thereby to sample an input signal in a time-interleaved manner, wherein for a given clock divider of the plurality of clock dividers, the synchronization signal corresponds to an output clock of a clock divider immediately upstream from the given clock divider.