公开(公告)号：US20240259022A1

公开(公告)日：2024-08-01

申请号：US18628805

申请日：2024-04-08

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Ying Wu ,  Weiliang Jing ,  Zhaozhao Hou ,  Renshi Fan ,  JEFFREY JUNHAO XU

IPC: H03K19/0944 ,  H03K3/037 ,  H03K19/20

CPC classification number: H03K19/0944 ,  H03K19/20 ,  H03K3/037

Abstract: A logic gate circuit includes a pull-up network, a pull-down network, a signal output end, at least one signal input end, a first voltage end, and a second voltage end. The pull-up network includes a first gate and a second gate. A first electrode of the first NFET and the first gate are connected to the first voltage end. A second electrode of the first NFET and the second gate are connected to the signal output end. The pull-down network includes a second NFET. The pull-down network is connected to the signal output end, the at least one signal input end, and the second voltage end. The pull-down network is configured to: control the second NFET based on a voltage of the at least one signal input end, and pull down a voltage of the signal output end by using a voltage of the second voltage end.