公开(公告)号：US10303124B2

公开(公告)日：2019-05-28

申请号：US15985252

申请日：2018-05-21

Applicant: Huawei Technologies Co., Ltd.

Inventor： Ying Wu ,  Robert Bogdan Staszewski ,  Yihong Mao

IPC: H03M3/00 ,  G04F3/00 ,  G04F10/00

Abstract: A time-to-digital converter includes: an input for receiving a time-domain input signal; an output for providing a digital output signal; a time register coupled to the input and to a first node; a time quantizer coupled to the time register for providing the digital output signal at the output; and a digital-to-time converter coupled to the output for providing a feed-back signal at the first node.

公开(公告)号：US10101709B2

公开(公告)日：2018-10-16

申请号：US15660514

申请日：2017-07-26

Applicant: Huawei Technologies Co., Ltd.

Inventor： Ying Wu ,  Robert Bogdan Staszewski ,  Yihong Mao

IPC: H03M1/50 ,  G04F10/00 ,  H03K5/135 ,  H03M1/12 ,  H03M1/00 ,  H03L7/089 ,  H03L7/081 ,  H03H19/00

Abstract: A time register includes: a pair of inputs coupled to a pair of input clocks; a pair of tri-state inverters for producing a pair of level signals; and a pair of outputs coupled to the level signals for producing a pair of output clocks, wherein the tri-state inverters are responsive to a pair of state signals and the pair of input clocks for holding or discharging the level signals.

公开(公告)号：US20240259022A1

公开(公告)日：2024-08-01

申请号：US18628805

申请日：2024-04-08

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Ying Wu ,  Weiliang Jing ,  Zhaozhao Hou ,  Renshi Fan ,  JEFFREY JUNHAO XU

IPC: H03K19/0944 ,  H03K3/037 ,  H03K19/20

CPC classification number: H03K19/0944 ,  H03K19/20 ,  H03K3/037

Abstract: A logic gate circuit includes a pull-up network, a pull-down network, a signal output end, at least one signal input end, a first voltage end, and a second voltage end. The pull-up network includes a first gate and a second gate. A first electrode of the first NFET and the first gate are connected to the first voltage end. A second electrode of the first NFET and the second gate are connected to the signal output end. The pull-down network includes a second NFET. The pull-down network is connected to the signal output end, the at least one signal input end, and the second voltage end. The pull-down network is configured to: control the second NFET based on a voltage of the at least one signal input end, and pull down a voltage of the signal output end by using a voltage of the second voltage end.

公开(公告)号：US09989928B2

公开(公告)日：2018-06-05

申请号：US15667114

申请日：2017-08-02

Applicant: Huawei Technologies Co., Ltd.

Inventor： Ying Wu ,  Robert Bogdan Staszewski ,  Yihong Mao

IPC: H03M1/50 ,  G04F10/00 ,  H03M3/00

CPC classification number: G04F10/005 ,  H03M3/414

Abstract: A time-to-digital converter includes: an input for receiving a time-domain input signal; an output for providing a digital output signal; a time register coupled to the input and to a first node; a time quantizer coupled to the time register for providing the digital output signal at the output; and a digital-to-time converter coupled to the output for providing a feed-back signal at the first node.