公开(公告)号：US20240206189A1

公开(公告)日：2024-06-20

申请号：US18589281

申请日：2024-02-27

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Wanliang Tan ,  Yuxing Li ,  Weigu Li ,  Jialin Cai ,  Hangbing Lv ,  JEFFREY JUNHAO XU

IPC: H10B53/20 ,  G11C11/22 ,  H01L21/28 ,  H01L29/51 ,  H01L29/78 ,  H10B51/10 ,  H10B51/20 ,  H10B53/10 ,  H10B53/30

CPC classification number: H10B53/20 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/2275 ,  H01L28/65 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/78391 ,  H10B51/10 ,  H10B51/20 ,  H10B53/10 ,  H10B53/30

Abstract: A ferroelectric memory includes a substrate and a plurality of memory cells formed on the substrate. Each memory cell includes a ferroelectric capacitor. The ferroelectric capacitor includes a first electrode and a second electrode, and a ferroelectric layer formed between the first electrode and the second electrode. The ferroelectric capacitor further includes a first isolation passivation layer formed between the first electrode and the ferroelectric layer, and a second isolation passivation layer formed between the second electrode and the ferroelectric layer. The first isolation passivation layer is configured to suppress diffusion of the oxygen element in the ferroelectric layer to the first electrode, and the second isolation passivation layer is configured to suppress diffusion of the oxygen element in the ferroelectric layer to the second electrode.

公开(公告)号：US20240259022A1

公开(公告)日：2024-08-01

申请号：US18628805

申请日：2024-04-08

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Ying Wu ,  Weiliang Jing ,  Zhaozhao Hou ,  Renshi Fan ,  JEFFREY JUNHAO XU

IPC: H03K19/0944 ,  H03K3/037 ,  H03K19/20

CPC classification number: H03K19/0944 ,  H03K19/20 ,  H03K3/037

Abstract: A logic gate circuit includes a pull-up network, a pull-down network, a signal output end, at least one signal input end, a first voltage end, and a second voltage end. The pull-up network includes a first gate and a second gate. A first electrode of the first NFET and the first gate are connected to the first voltage end. A second electrode of the first NFET and the second gate are connected to the signal output end. The pull-down network includes a second NFET. The pull-down network is connected to the signal output end, the at least one signal input end, and the second voltage end. The pull-down network is configured to: control the second NFET based on a voltage of the at least one signal input end, and pull down a voltage of the signal output end by using a voltage of the second voltage end.

公开(公告)号：US20240130139A1

公开(公告)日：2024-04-18

申请号：US18359823

申请日：2023-07-26

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Zhaozhao Hou ,  Sitong Bu ,  Yichen Fang ,  Yu Zhang ,  JEFFREY JUNHAO XU

IPC: H10B53/30 ,  G11C11/22

CPC classification number: H10B53/30 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/2275

Abstract: A ferroelectric memory includes at least one storage cell. Each storage cell includes a transistor, a first ferroelectric capacitor, and at least one voltage divider capacitor. The transistor includes a gate electrode, a source electrode, and a drain electrode. One electrode of the first ferroelectric capacitor is connected to the gate electrode. The other electrode of the first ferroelectric capacitor is connected to a word line. One electrode of each voltage divider capacitor in the at least one voltage divider capacitor is connected to the gate electrode, and the other electrode of each voltage divider capacitor in the at least one voltage divider capacitor is connected to the source electrode.