公开(公告)号：US20240259022A1

公开(公告)日：2024-08-01

申请号：US18628805

申请日：2024-04-08

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Ying Wu ,  Weiliang Jing ,  Zhaozhao Hou ,  Renshi Fan ,  JEFFREY JUNHAO XU

IPC: H03K19/0944 ,  H03K3/037 ,  H03K19/20

CPC classification number: H03K19/0944 ,  H03K19/20 ,  H03K3/037

Abstract: A logic gate circuit includes a pull-up network, a pull-down network, a signal output end, at least one signal input end, a first voltage end, and a second voltage end. The pull-up network includes a first gate and a second gate. A first electrode of the first NFET and the first gate are connected to the first voltage end. A second electrode of the first NFET and the second gate are connected to the signal output end. The pull-down network includes a second NFET. The pull-down network is connected to the signal output end, the at least one signal input end, and the second voltage end. The pull-down network is configured to: control the second NFET based on a voltage of the at least one signal input end, and pull down a voltage of the signal output end by using a voltage of the second voltage end.

公开(公告)号：US20240130139A1

公开(公告)日：2024-04-18

申请号：US18359823

申请日：2023-07-26

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Zhaozhao Hou ,  Sitong Bu ,  Yichen Fang ,  Yu Zhang ,  JEFFREY JUNHAO XU

IPC: H10B53/30 ,  G11C11/22

CPC classification number: H10B53/30 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/2275

Abstract: A ferroelectric memory includes at least one storage cell. Each storage cell includes a transistor, a first ferroelectric capacitor, and at least one voltage divider capacitor. The transistor includes a gate electrode, a source electrode, and a drain electrode. One electrode of the first ferroelectric capacitor is connected to the gate electrode. The other electrode of the first ferroelectric capacitor is connected to a word line. One electrode of each voltage divider capacitor in the at least one voltage divider capacitor is connected to the gate electrode, and the other electrode of each voltage divider capacitor in the at least one voltage divider capacitor is connected to the source electrode.

公开(公告)号：US20230352552A1

公开(公告)日：2023-11-02

申请号：US18350348

申请日：2023-07-11

Applicant: Huawei Technologies Co., Ltd.

Inventor： Luming Fan ,  Yanxiang Liu ,  Jeffrey Junhao Xu ,  Francis Lionel Benistant ,  Zhaozhao Hou

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/775 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/66439 ,  H01L29/78696 ,  H01L29/66545

Abstract: A memory includes a storage array, at least one source line, at least one word line, and at least one bit line. The storage array includes a plurality of gate-all-around field-effect transistors. The at least one word line is connected to gates of the plurality of gate-all-around field-effect transistors. The at least one source line is connected to sources of the plurality of gate-all-around field-effect transistors. The at least one bit line is connected to drains of the plurality of gate-all-around field-effect transistors. A material of a nanowire of the gate-all-around field-effect transistor is silicon germanium (SiGe). For a next-generation logic process (for example, a GAA process), a storage array including a gate-all-around field-effect transistor manufactured by using a same process as a logic process is used in a memory so that the memory can be compatible with the logic process.