公开(公告)号：US10796774B2

公开(公告)日：2020-10-06

申请号：US16120780

申请日：2018-09-04

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Liang Shi ,  Yejia Di ,  Hsing Mean Sha ,  Yuangang Wang ,  Dongfang Shan

IPC: G11C16/34 ,  G06F11/10 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C29/52 ,  G11C11/56 ,  H01L29/788

Abstract: A flash memory controller refreshes memory blocks in a flash memory device by setting different refresh cycles for individual memory blocks in the flash memory device. The flash memory controller records a number of erase operations performed on each memory block of the flash memory device. Upon detecting that a bit error rate of a memory block is greater than a preset threshold, the flash memory controller determines a refresh cycle for the memory block based on recorded number of erase operations performed on the memory block, and then refreshes the memory block according to the refresh cycle.

公开(公告)号：US20180357013A1

公开(公告)日：2018-12-13

申请号：US16105723

申请日：2018-08-20

Applicant: HUAWEI TECHNOLOGIES CO.,LTD.

Inventor： Liang Shi ,  Chun Xue ,  Qiao Li ,  Dongfang Shan ,  Jun Xu ,  Yuangang Wang

IPC: G06F3/06

Abstract: A method for accessing a flash memory device and a flash memory device. After receiving a write request for an address, a flash memory controller obtains an indicator of the address, where the indicator indicates a last access type of the address, which might be a write operation or a read operation. When determining the indicator indicates a write operation, which means the access type for the address is normally write operation, to save time, the flash memory controller perform a fast-write operation on the address, when the indicator indicates a read operation, which means there might be plenty of read operations on the address, to facilitate future read operation, the controller performs a slow-write operation on the address.

公开(公告)号：US10732898B2

公开(公告)日：2020-08-04

申请号：US16105723

申请日：2018-08-20

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Liang Shi ,  Chun Xue ,  Qiao Li ,  Dongfang Shan ,  Jun Xu ,  Yuangang Wang

IPC: G06F3/06 ,  G11C11/56 ,  G06F12/02 ,  G11C16/28 ,  G11C16/26

Abstract: A method for accessing a flash memory device and a flash memory device. After receiving a write request for an address, a flash memory controller obtains an indicator of the address, where the indicator indicates a last access type of the address, which might be a write operation or a read operation. When determining the indicator indicates a write operation, which means the access type for the address is normally write operation, to save time, the flash memory controller perform a fast-write operation on the address, when the indicator indicates a read operation, which means there might be plenty of read operations on the address, to facilitate future read operation, the controller performs a slow-write operation on the address.

公开(公告)号：US20180374546A1

公开(公告)日：2018-12-27

申请号：US16120780

申请日：2018-09-04

Applicant: HUAWEI TECHNOLOGIES CO.,LTD.

Inventor： Liang Shi ,  Yejia Di ,  Hsing Mean SHA ,  Yuangang Wang ,  Dongfang Shan

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/14 ,  G11C16/26 ,  G11C16/10 ,  G06F11/10 ,  G11C29/52

Abstract: A flash memory controller refreshes memory blocks in a flash memory device by setting different refresh cycles for individual memory blocks in the flash memory device. The flash memory controller records a number of erase operations performed on each memory block of the flash memory device. Upon detecting that a bit error rate of a memory block is greater than a preset threshold, the flash memory controller determines a refresh cycle for the memory block based on recorded number of erase operations performed on the memory block, and then refreshes the memory block according to the refresh cycle.