公开(公告)号：US20070128775A1

公开(公告)日：2007-06-07

申请号：US11607600

申请日：2006-12-01

申请人： Taek-Soo Jeon ,  Hag-ju Cho ,  Hye-Lan Lee ,  Yu-Gyun Shin ,  Sang-Bom Kang

发明人： Taek-Soo Jeon ,  Hag-ju Cho ,  Hye-Lan Lee ,  Yu-Gyun Shin ,  Sang-Bom Kang

IPC分类号： H01L21/84

CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518

摘要： A method of manufacturing a gate electrode of a MOS transistor including a tungsten carbon nitride layer is disclosed. After a high dielectric layer is formed on a substrate, a source gas including tungsten amine derivative flows onto the high dielectric layer. A tungsten carbon nitride layer is formed on the high dielectric layer by decomposing the source gas. Thereafter, a gate electrode is formed by patterning the tungsten carbon nitride layer. According to the present invention, a gate electrode having a work function of over 4.9 eV is formed.

摘要翻译： 公开了一种制造包括氮化钨层的MOS晶体管的栅电极的方法。 在基板上形成高电介质层之后，包含钨胺衍生物的源气体流到高电介质层上。 通过分解源气体，在高电介质层上形成碳氮化钨层。 此后，通过图案化氮化碳钨层来形成栅电极。 根据本发明，形成功函数为4.9eV以上的栅电极。

公开(公告)号：US20070111453A1

公开(公告)日：2007-05-17

申请号：US11497998

申请日：2006-08-01

申请人： Hye-Lan Lee ,  Hag-Ju Cho ,  Taek-Soo Jeon ,  Yu-Gyun Shin ,  Sang-Bom Kang

发明人： Hye-Lan Lee ,  Hag-Ju Cho ,  Taek-Soo Jeon ,  Yu-Gyun Shin ,  Sang-Bom Kang

IPC分类号： H01L21/336 ,  H01L29/94

CPC分类号： H01L21/823842

摘要： In a semiconductor device with dual gates and a method of manufacturing the same, a dielectric layer and first and second metallic conductive layers are successively formed on the semiconductor substrate having first and second regions. The second metallic conductive layer which is formed on the first metallic conductive layer of the second region is etched to form a metal pattern. The first metallic conductive layer is etched using the metal pattern as an etching mask. A polysilicon layer is formed on the dielectric layer and the metal pattern. The first gate electrode is formed by etching portions of the polysilicon layer, the metal pattern, and the first metallic conductive layer of the first region. The second gate electrode is formed by etching a portion of the polysilicon layer formed directly on the dielectric layer of the second region.

摘要翻译： 在具有双栅极的半导体器件及其制造方法中，在具有第一和第二区域的半导体衬底上依次形成电介质层和第一和第二金属导电层。 形成在第二区域的第一金属导电层上的第二金属导电层被蚀刻以形成金属图案。 使用金属图案作为蚀刻掩模蚀刻第一金属导电层。 在电介质层和金属图案上形成多晶硅层。 第一栅极通过蚀刻第一区域的多晶硅层，金属图案和第一金属导电层的部分而形成。 通过蚀刻直接形成在第二区域的电介质层上的多晶硅层的一部分来形成第二栅电极。

公开(公告)号：US20070082415A1

公开(公告)日：2007-04-12

申请号：US11497972

申请日：2006-08-01

申请人： Taek-Soo Jeon ,  Yu-Gyun Shin ,  Sang-Bom Kang ,  Hag-Ju Cho ,  Hye-Lan Lee ,  Sang-Yong Kim

发明人： Taek-Soo Jeon ,  Yu-Gyun Shin ,  Sang-Bom Kang ,  Hag-Ju Cho ,  Hye-Lan Lee ,  Sang-Yong Kim

IPC分类号： H01L21/00

CPC分类号： H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/78

摘要： A semiconductor device having a dual gate is formed on a substrate having a dielectric layer. A first metallic conductive layer is formed on the dielectric layer to a first thickness, and annealed to have a reduced etching rate. A second metallic conductive layer is formed on the first metallic conductive layer to a second thickness that is greater than the first thickness. A portion of the second metallic conductive layer formed in a second area of the substrate is removed using an etching selectivity. A first gate structure having a first metallic gate including the first and the second metallic conductive layers is formed in a first area of the substrate. A second gate structure having a second metallic gate is formed in the second area. A gate dielectric layer is not exposed to an etching chemical due to the first metallic conductive layer, so its dielectric characteristics are not degraded.

摘要翻译： 具有双栅极的半导体器件形成在具有电介质层的衬底上。 在电介质层上形成第一金属导电层至第一厚度，并且退火以降低蚀刻速率。 在第一金属导电层上形成第二金属导电层至大于第一厚度的第二厚度。 使用蚀刻选择性去除在衬底的第二区域中形成的第二金属导电层的一部分。 具有包括第一和第二金属导电层的第一金属栅极的第一栅极结构形成在衬底的第一区域中。 具有第二金属栅极的第二栅极结构形成在第二区域中。 由于第一金属导电层，栅极电介质层不暴露于蚀刻化学品，因此其介电特性不劣化。

公开(公告)号：US20070026596A1

公开(公告)日：2007-02-01

申请号：US11492400

申请日：2006-07-25

申请人： Hag-Ju Cho ,  Taek-Soo Jeon ,  Hye-Lan Lee ,  Yu-Gyun Shin ,  Sang-Bom Kang

发明人： Hag-Ju Cho ,  Taek-Soo Jeon ,  Hye-Lan Lee ,  Yu-Gyun Shin ,  Sang-Bom Kang

IPC分类号： H01L21/8234

CPC分类号： H01L21/823828 ,  H01L21/823835 ,  H01L21/823842

摘要： In a gate structure and a method of forming the same, a first conductive pattern is formed on a substrate and comprises a metal-containing material. A second conductive pattern is formed on the first conductive pattern, and the second conductive pattern comprises metal and silicon. A third conductive pattern is formed on the second conductive pattern, and the third conductive pattern comprises polysilicon. A gate conductive pattern of an n-type metal-oxide semiconductor (NMOS) transistor, a p-type MOS (PMOS) transistor and a complementary MOS (CMOS) transistor includes the gate structure. The second conductive pattern is interposed between the first and third conductive patterns and the third conductive pattern is prevented from making direct contact with the first conductive pattern, so that polysilicon in the third conductive pattern is sufficiently prevented from being chemically reacted with the metal in the first conductive pattern in advance, thereby improving electrical characteristics of the transistor.

摘要翻译： 在栅极结构及其形成方法中，第一导电图案形成在基板上并且包括含金属的材料。 在第一导电图案上形成第二导电图案，并且第二导电图案包括金属和硅。 在第二导电图案上形成第三导电图案，并且第三导电图案包括多晶硅。 n型金属氧化物半导体（NMOS）晶体管，p型MOS（PMOS）晶体管和互补MOS（CMOS）晶体管的栅极导电图案包括栅极结构。 第二导电图案插入在第一和第三导电图案之间，并且防止第三导电图案与第一导电图案直接接触，使得充分防止第三导电图案中的多晶硅与金属在化学反应中 第一导电图案，从而改善晶体管的电特性。

公开(公告)号：US20060273344A1

公开(公告)日：2006-12-07

申请号：US11400560

申请日：2006-04-07

申请人： Hye-Lan Lee ,  Yu-Gyun Shin ,  Sang-Bom Kang ,  Hag-Ju Cho ,  Seong-Geon Pack ,  Taek-Soo Jeon

发明人： Hye-Lan Lee ,  Yu-Gyun Shin ,  Sang-Bom Kang ,  Hag-Ju Cho ,  Seong-Geon Pack ,  Taek-Soo Jeon

IPC分类号： H01L29/74

CPC分类号： H01L21/823842 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

摘要： A semiconductor device has two transistors of different structure from each other. One of transistors is P-type and the other is N-type. One of the transistors includes a gate structure in which a polysilicon layer contacts a gate insulation film while the other transistor includes a gate structure in which a metal layer contacts a gate insulation film.

公开(公告)号：US20060030097A1

公开(公告)日：2006-02-09

申请号：US11183651

申请日：2005-07-18

申请人： Taek-Soo Jeon ,  Yu-Gyun Shin ,  Sang-Bom Kang ,  Hong-Bae Park ,  Hag-Ju Cho ,  Hye-Lan Lee ,  Beom-Jun Jin ,  Seong-Geon Park

发明人： Taek-Soo Jeon ,  Yu-Gyun Shin ,  Sang-Bom Kang ,  Hong-Bae Park ,  Hag-Ju Cho ,  Hye-Lan Lee ,  Beom-Jun Jin ,  Seong-Geon Park

IPC分类号： H01L21/8238

CPC分类号： H01L21/823842

摘要： A method of forming transistor gate structures in an integrated circuit device can include forming a high-k gate insulating layer on a substrate including a first region to include PMOS transistors and a second region to include NMOS transistors. A polysilicon gate layer can be formed on the high-k gate insulating layer in the first and second regions. A metal silicide gate layer can be formed directly on the high-k gate insulating layer in the first region and avoiding forming the metal-silicide in the second region. Related gate structures are also disclosed.

摘要翻译： 在集成电路器件中形成晶体管栅结构的方法可以包括在包括PMOS晶体管的第一区域的衬底上形成高k栅极绝缘层，以及包括NMOS晶体管的第二区域。 可以在第一和第二区域的高k栅极绝缘层上形成多晶硅栅极层。 可以在第一区域中的高k栅极绝缘层上直接形成金属硅化物栅极层，并且避免在第二区域中形成金属硅化物。 还公开了相关门结构。

公开(公告)号：US07494859B2

公开(公告)日：2009-02-24

申请号：US11400243

申请日：2006-04-10

申请人： Hag-Ju Cho ,  Taek-Soo Jeon ,  Hye-Lan Lee ,  Sang-Bom Kang ,  Yu-Gyun Shin

发明人： Hag-Ju Cho ,  Taek-Soo Jeon ,  Hye-Lan Lee ,  Sang-Bom Kang ,  Yu-Gyun Shin

IPC分类号： H01L21/8238

CPC分类号： H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4958 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

摘要： A semiconductor device comprising a semiconductor substrate having a first impurity region and a second impurity region, a first gate pattern formed on the first impurity region, and a second gate pattern formed on the second impurity region is disclosed. The first gate pattern comprises a first gate insulation layer pattern, a metal layer pattern having a first thickness, and a first polysilicon layer pattern. The second gate pattern comprises a second gate insulation layer pattern, a metal silicide layer pattern having a second thickness smaller than the first thickness, and a second polysilicon layer pattern. The metal silicide layer pattern is formed from a material substantially the same as the material from which the metal layer pattern is formed. A method for manufacturing the semiconductor device is also disclosed.

摘要翻译： 一种半导体器件，包括具有第一杂质区和第二杂质区的半导体衬底，形成在第一杂质区上的第一栅极图案和形成在第二杂质区上的第二栅极图案。 第一栅极图案包括第一栅极绝缘层图案，具有第一厚度的金属层图案和第一多晶硅层图案。 第二栅极图案包括第二栅极绝缘层图案，具有小于第一厚度的第二厚度的金属硅化物层图案和第二多晶硅层图案。 金属硅化物层图案由与形成金属层图案的材料基本相同的材料形成。 还公开了一种半导体器件的制造方法。

公开(公告)号：US20060226470A1

公开(公告)日：2006-10-12

申请号：US11400243

申请日：2006-04-10

申请人： Hag-Ju Cho ,  Taek-Soo Jeon ,  Hye-Lan Lee ,  Sang-Bom Kang ,  Yu-Gyun Shin

发明人： Hag-Ju Cho ,  Taek-Soo Jeon ,  Hye-Lan Lee ,  Sang-Bom Kang ,  Yu-Gyun Shin

IPC分类号： H01L29/788 ,  H01L29/76 ,  H01L21/8238 ,  H01L21/336

CPC分类号： H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4958 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

摘要： A semiconductor device comprising a semiconductor substrate having a first impurity region and a second impurity region, a first gate pattern formed on the first impurity region, and a second gate pattern formed on the second impurity region is disclosed. The first gate pattern comprises a first gate insulation layer pattern, a metal layer pattern having a first thickness, and a first polysilicon layer pattern. The second gate pattern comprises a second gate insulation layer pattern, a metal silicide layer pattern having a second thickness smaller than the first thickness, and a second polysilicon layer pattern. The metal silicide layer pattern is formed from a material substantially the same as the material from which the metal layer pattern is formed. A method for manufacturing the semiconductor device is also disclosed.

公开(公告)号：US07892958B2

公开(公告)日：2011-02-22

申请号：US12422849

申请日：2009-04-13

申请人： Hye-Lan Lee ,  Yu-Gyun Shin ,  Sang-Bom Kang ,  Hag-Ju Cho ,  Seong-Geon Park ,  Taek-Soo Jeon

发明人： Hye-Lan Lee ,  Yu-Gyun Shin ,  Sang-Bom Kang ,  Hag-Ju Cho ,  Seong-Geon Park ,  Taek-Soo Jeon

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/823842 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

摘要： A semiconductor device has two transistors of different structure from each other. One of transistors is P-type and the other is N-type. One of the transistors includes a gate structure in which a polysilicon layer contacts a gate insulation film while the other transistor includes a gate structure in which a metal layer contacts a gate insulation film.

摘要翻译： 半导体器件具有彼此不同结构的两个晶体管。 晶体管中的一个是P型，另一个是N型。 一个晶体管包括其中多晶硅层接触栅极绝缘膜的栅极结构，而另一个晶体管包括其中金属层与栅极绝缘膜接触的栅极结构。

公开(公告)号：US20100193875A1

公开(公告)日：2010-08-05

申请号：US12759284

申请日：2010-04-13

申请人： Hye-Lan Lee ,  Hag-Ju Cho ,  Taek-Soo Jeon ,  Yu-Gyun Shin ,  Sang-Bom Kang

发明人： Hye-Lan Lee ,  Hag-Ju Cho ,  Taek-Soo Jeon ,  Yu-Gyun Shin ,  Sang-Bom Kang

IPC分类号： H01L27/092

CPC分类号： H01L21/823842

摘要： In a semiconductor device with dual gates and a method of manufacturing the same, a dielectric layer and first and second metallic conductive layers are successively formed on the semiconductor substrate having first and second regions. The second metallic conductive layer which is formed on the first metallic conductive layer of the second region is etched to form a metal pattern. The first metallic conductive layer is etched using the metal pattern as an etching mask. A polysilicon layer is formed on the dielectric layer and the metal pattern. The first gate electrode is formed by etching portions of the polysilicon layer, the metal pattern, and the first metallic conductive layer of the first region. The second gate electrode is formed by etching a portion of the polysilicon layer formed directly on the dielectric layer of the second region.

摘要翻译： 在具有双栅极的半导体器件及其制造方法中，在具有第一和第二区域的半导体衬底上依次形成电介质层和第一和第二金属导电层。 形成在第二区域的第一金属导电层上的第二金属导电层被蚀刻以形成金属图案。 使用金属图案作为蚀刻掩模蚀刻第一金属导电层。 在电介质层和金属图案上形成多晶硅层。 第一栅极通过蚀刻第一区域的多晶硅层，金属图案和第一金属导电层的部分而形成。 通过蚀刻直接形成在第二区域的电介质层上的多晶硅层的一部分来形成第二栅电极。