公开(公告)号：US6080666A

公开(公告)日：2000-06-27

申请号：US274596

申请日：1999-03-23

申请人： Hal Lee ,  Der-Yuan Wu

发明人： Hal Lee ,  Der-Yuan Wu

IPC分类号： H01L21/768 ,  H01L21/44 ,  H01L21/4763

CPC分类号： H01L21/76838 ,  H01L21/76885

摘要： A method for increasing landing pad area is disclosed. Firstly, providing a fundamental structure, wherein shallow trench isolation (STI) is used and acting as an electrical isolation inside of substrate. Moreover, there are at least two gates with an isolation layer on top of the substrate and covered with a dielectric layer. Between the neighboring gates there is a contact hole that penetrates the dielectric layer from the top of the dielectric layer to the substrate. Taking this fundamental structure as the starting point for forming a conductor within the contact hole. Etching back the dielectric layer and exposing its top surface and a portion of sidewalls. Finally, a protection layer on top of the exposed portion of sidewalls of the conductor is formed in order to expand the landing pad area. After all, one would still be able to increase the landing pad area even though the distance between two gates is rather small. This method can solve all the puzzles caused by alignment accuray shift during post-process.

摘要翻译： 公开了一种增加着陆垫面积的方法。 首先，提供一种基本结构，其中使用浅沟槽隔离（STI）并且用作衬底内的电隔离。 此外，在衬底的顶部上至少有两个具有隔离层的栅极，并且被绝缘层覆盖。 在相邻的浇口之间有一个接触孔，该接触孔从电介质层的顶部到基底穿透电介质层。 将该基本结构作为在接触孔内形成导体的起点。 蚀刻介电层并暴露其顶表面和一部分侧壁。 最后，形成了在导体的侧壁的暴露部分的顶部上的保护层，以便扩大着陆焊盘区域。 毕竟，即使两个门之间的距离相当小，仍然可以增加着陆垫区域。 该方法可以解决后期处理中对准精度偏移引起的所有难题。

公开(公告)号：US06833318B2

公开(公告)日：2004-12-21

申请号：US10065803

申请日：2002-11-20

申请人： Chun-Jen Weng ,  Juan-Yi Chen ,  Hong-Tsz Pan ,  Cedric Lee ,  Der-Yuan Wu ,  Jackson Lin ,  Yeong-Song Yen ,  Lawrence Lin ,  Ying-Chung Tseng

发明人： Chun-Jen Weng ,  Juan-Yi Chen ,  Hong-Tsz Pan ,  Cedric Lee ,  Der-Yuan Wu ,  Jackson Lin ,  Yeong-Song Yen ,  Lawrence Lin ,  Ying-Chung Tseng

IPC分类号： H01L214763

CPC分类号： H01L21/76808 ,  H01L21/31144

摘要： A gap-filling process is provided. A substrate having a dielectric layer thereon is provided. The dielectric layer has an opening therein. A gap-filling material layer is formed over the dielectric layer and inside the opening. A portion of the gap-filling material is removed from the gap-filling material layer to expose the dielectric layer. A gap-filling material treatment of the surface of the gap-filling material layer and the dielectric layer is carried out to planarize the gap-filling material layer so that a subsequently formed bottom anti-reflection coating or material layer over the gap-filling material layer can have a high degree of planarity.

摘要翻译： 提供间隙填充过程。 提供其上具有介电层的基板。 电介质层中有一个开口。 在电介质层和开口内部形成间隙填充材料层。 间隙填充材料的一部分从间隙填充材料层去除以暴露电介质层。 进行间隙填充材料层和电介质层的表面的间隙填充材料处理以使间隙填充材料层平坦化，从而在间隙填充材料上形成随后形成的底部抗反射涂层或材料层 层可以具有高度的平面度。

公开(公告)号：US06667534B1

公开(公告)日：2003-12-23

申请号：US10197861

申请日：2002-07-19

申请人： Der-Yuan Wu ,  Chiu-Te Lee

发明人： Der-Yuan Wu ,  Chiu-Te Lee

IPC分类号： H01L2943

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： A copper fuse structure and the method for fabricating the same is disclosed in this present invention. By employing an inner copper metal layer as a fuse, the copper fuse according to this invention can be easily zipped with a laser repair tool. Furthermore, the openings on a bonding pad and the fuse of the semiconductor structure can be identified with the method according to this invention. Moreover, in contrast of the fuse formed with an upper aluminum layer in the prior art, the cost of the fuse manufacturing is lower in the method according to this invention by fabricating the fuse with an inner copper layer.

摘要翻译： 在本发明中公开了一种铜熔丝结构及其制造方法。 通过使用内部铜金属层作为保险丝，根据本发明的铜熔丝可以用激光修复工具容易地拉链。 此外，可以使用根据本发明的方法来识别焊盘上的开口和半导体结构的熔丝。 此外，与现有技术中的上铝层形成的保险丝相反，根据本发明的方法，通过制造具有内铜层的保险丝，熔丝制造的成本较低。

公开(公告)号：US6121085A

公开(公告)日：2000-09-19

申请号：US9508

申请日：1998-01-20

申请人： Chia-Wen Liang ,  Sun-Chieh Chien ,  Der-Yuan Wu ,  Jason Jenq

发明人： Chia-Wen Liang ,  Sun-Chieh Chien ,  Der-Yuan Wu ,  Jason Jenq

IPC分类号： H01L21/8242 ,  H01L21/20

CPC分类号： H01L27/10852

摘要： A method of making contact openings for memory cell units of DRAM IC devices is disclosed. The contact opening is used to connect the cell transistor source/drain terminal to the storage capacitor electrode located substantially above. The method includes the step of first patterning the initial opening in a shielding layer for the contact opening. The diameter of the initial opening is then reduced by the formation of sidewall spacers in initial opening. The initial opening in the shielding layer is then used to implement the etching for the formation of the contact opening. Due to reduced size of the contact opening, short-circuiting situations arising between the via formed in the contact opening and the bit lines next to the via as a result of misalignment in the process of fabrication can be reduced, thereby improving the device fabrication yield rates.

摘要翻译： 公开了一种制造DRAM IC器件的存储单元的接触开口的方法。 接触开口用于将单元晶体管源极/漏极端子连接到大致位于上方的存储电容器电极。 该方法包括首先在接触开口的屏蔽层中构图初始开口的步骤。 然后通过在初始开口中形成侧壁间隔来减小初始开口的直径。 然后使用屏蔽层中的初始开口来实现用于形成接触开口的蚀刻。 由于接触开口的尺寸减小，可以减少在制造工艺中由于在接触开口中形成的通孔与通孔旁边的位线之间产生的短路情况，从而提高器件的制造成品率 价格。

公开(公告)号：US06753244B2

公开(公告)日：2004-06-22

申请号：US10426787

申请日：2003-05-01

申请人： Der-Yuan Wu ,  Chiu-Te Lee

发明人： Der-Yuan Wu ,  Chiu-Te Lee

IPC分类号： H01L2144

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： A copper fuse structure and the method for fabricating the same is disclosed in this present invention. By employing an inner copper metal layer as a fuse, the copper fuse according to this invention can be easily zipped with a laser repair tool. Furthermore, the openings on a bonding pad and the fuse of the semiconductor structure can be identified with the method according to this invention. Moreover, in contrast of the fuse formed with an upper aluminum layer in the prior art, the cost of the fuse manufacturing is lower in the method according to this invention by fabricating the fuse with an inner copper layer.

摘要翻译： 在本发明中公开了一种铜熔丝结构及其制造方法。 通过使用内部铜金属层作为保险丝，根据本发明的铜熔丝可以用激光修复工具容易地拉链。 此外，可以使用根据本发明的方法来识别焊盘上的开口和半导体结构的熔丝。 此外，与现有技术中的上铝层形成的保险丝相反，根据本发明的方法，通过制造具有内铜层的保险丝，熔丝制造的成本较低。

公开(公告)号：US06392924B1

公开(公告)日：2002-05-21

申请号：US09828376

申请日：2001-04-06

申请人： Chih-Cheng Liu ,  Der-Yuan Wu

发明人： Chih-Cheng Liu ,  Der-Yuan Wu

IPC分类号： G11C1100

CPC分类号： H01L27/222 ,  G11C11/15 ,  G11C11/16

摘要： The array includes: a plurality of pseudo spin valve (PSV) cells; a plurality of parallel bit lines, wherein a plurality of bit lines are straight lines and located under the plurality of pseudo spin valve (PSV) cells; a plurality of parallel word lines, wherein a plurality of word lines are continuous-bended lines having a first straight line, a second straight line and a third straight line. These straight lines of the word lines are orthogonal each other, wherein the first straight line and the third straight line are parallel. The first straight line and the third straight line are individually orthogonal with the direction of the bit lines. Furthermore, the second straight lines of the word lines are individually located on the pseudo spin valve (PSV) cells, and the second straight lines are parallel with the direction of the bit lines, so as to increase the magnetresistance ratio.

摘要翻译： 阵列包括：多个假自旋阀（PSV）单元; 多个并行位线，其中多个位线是直线并位于所述多个伪自旋阀（PSV）单元之下; 多个平行字线，其中多个字线是具有第一直线，第二直线和第三直线的连续弯曲线。 字线的这些直线彼此正交，其中第一直线和第三直线平行。 第一直线和第三直线与位线的方向分别正交。 此外，字线的第二直线分别位于伪自旋阀（PSV）单元上，并且第二直线与位线的方向平行，以增加磁阻比。

公开(公告)号：US6051507A

公开(公告)日：2000-04-18

申请号：US172406

申请日：1998-10-14

申请人： J. S. Jason Jenq ,  Der-Yuan Wu

发明人： J. S. Jason Jenq ,  Der-Yuan Wu

IPC分类号： H01L21/02 ,  H01L21/00

CPC分类号： H01L28/82 ,  H01L28/84 ,  H01L28/92

摘要： The invention provides a method of fabricating a capacitor with high capacitance. A substrate having word lines and bit lines is provided, and a dielectric layer is formed to cover the substrate. A contact window is formed in the dielectric layer to expose an active region. A conductive layer is formed to fill the contact window to connect with the active region. An insulating layer is formed on the conductive layer and the insulating layer and the conductive layer are defined. A hemispherical grained-Si (HSG-Si) layer is then formed on the substrate. An etching process is performed on the HSG-Si layer to expose the dielectric layer using a portion of the insulating layer as a mask. The insulating layer is removed. A storage node with a gear toothed profile is then formed.

摘要翻译： 本发明提供一种制造具有高电容的电容器的方法。 提供具有字线和位线的基板，并且形成介电层以覆盖基板。 在电介质层中形成接触窗口以暴露活性区域。 形成导电层以填充接触窗口以与有源区域连接。 在导电层上形成绝缘层，并且限定绝缘层和导电层。 然后在基板上形成半球形的Si（HSG-Si）层。 使用绝缘层的一部分作为掩模，在HSG-Si层上进行蚀刻处理以使介电层露出。 绝缘层被去除。 然后形成具有齿轮齿廓的存储节点。

公开(公告)号：US5854106A

公开(公告)日：1998-12-29

申请号：US6225

申请日：1998-01-12

申请人： Der-Yuan Wu

发明人： Der-Yuan Wu

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： A method is provided for use on a DRAM (dynamic random access memory) device for forming a data storage capacitor with a wide electrode area, and thus a high capacitance, for the DRAM device. The high capacitance allows the data storage capacitor to preserve high data retaining capability when the DRAM device is downsized for high integration. The method is characterized in the forming of silicon-nitride based sidewall spacers in openings formed in oxide layers that allows the subsequently formed contact window to be formed with a reduced width, thereby preventing the subsequent etching process to damage the nearby polysilicon-based bit lines and gate electrodes due to misalignment in the etching. Moreover, the method allows the resultant data storage capacitor to have a wide electrode area that helps increase the capacitance thereof, thereby allowing the DRAM device to preserve a high and reliable data retaining capability to the data stored therein.

摘要翻译： 提供了一种用于DRAM（动态随机存取存储器）器件的方法，用于形成具有宽电极面积的数据存储电容器，因此用于DRAM器件的高电容。 当DRAM器件小型化以实现高集成度时，高电容允许数据存储电容器保持高数据保持能力。 该方法的特征在于在氧化物层中形成的开口中形成氮化硅基侧壁间隔物，其允许随后形成的接触窗口以减小的宽度形成，从而防止随后的蚀刻工艺损坏附近的多晶硅基位线 和栅电极由于在蚀刻中的未对准。 此外，该方法允许所得到的数据存储电容器具有有助于增加其电容的宽电极面积，从而允许DRAM器件保存对其中存储的数据的高且可靠的数据保留能力。

公开(公告)号：US06281069B1

公开(公告)日：2001-08-28

申请号：US09689395

申请日：2000-10-12

申请人： Der-Yuan Wu ,  Chiu-Te Lee

发明人： Der-Yuan Wu ,  Chiu-Te Lee

IPC分类号： H01L218242

CPC分类号： H01L27/10867

摘要： A method is for forming a deep trench capacitor under a shallow trench isolation structure. The method first provides a substrate and sequentially forms a pad oxide, a first mask layer, and a second mask layer over the substrate. A photoresist layer formed on the second mask layer has a thicker portion and a thinner portion, location of the thinner portion is the predetermined location to be formed an STI structure thereunder. A photoresist opening is between the thicker portion and the thinner portion to form a deep trench in the substrate by etching. The photoresist layer is removed, wherein the second mask layer under the thinner portion of the photoresist layer is also removed to expose the first mask layer. A deep trench capacitor is formed on the lower portion of the deep trench. A dielectric collar layer is formed on the sidewall of the deep trench. A selective growth polysilicon layer is formed to fill the deep trench with a height higher than the substrate surface. A self-aligned STI opening is formed to expose a portion of the dielectric collar layer having a contact with the deep trench. Then, a STI structure is formed to fill the STI opening.

摘要翻译： 一种在浅沟槽隔离结构下形成深沟槽电容器的方法。 该方法首先提供衬底并且在衬底上顺序地形成衬垫氧化物，第一掩模层和第二掩模层。 形成在第二掩模层上的光致抗蚀剂层具有较厚部分和较薄部分，较薄部分的位置是要形成其下方STI结构的预定位置。 光致抗蚀剂开口位于较厚部分和较薄部分之间，以通过蚀刻在衬底中形成深沟槽。 去除光致抗蚀剂层，其中除去光致抗蚀剂层较薄部分下方的第二掩模层以露出第一掩模层。 深沟槽电容器形成在深沟槽的下部。 在深沟槽的侧壁上形成介电轴环层。 形成选择性生长多晶硅层，以填充高于衬底表面的高度的深沟槽。 形成自对准的STI开口以暴露具有与深沟槽接触的介电套环层的一部分。 然后，形成STI结构以填充STI开口。

公开(公告)号：US06204109B1

公开(公告)日：2001-03-20

申请号：US09309973

申请日：1999-05-11

申请人： Der-Yuan Wu

发明人： Der-Yuan Wu

IPC分类号： H01L218234

CPC分类号： H01L28/92 ,  H01L27/10814

摘要： A method for forming a cylindrical capacitor of a dynamic random access memory cell is disclosed. The method includes firstly providing a semiconductor substrate having a dielectric layer thereon, at least one contact hole formed in the dielectric layer, wherein the contact hole extends from the top surface of the dielectric layer to the surface of the substrate. Next, a conductive layer is formed on the dielectric layer, and a blocking layer is further formed on the conductive layer. The conductive layer fills the contact hole, wherein at least one trench is formed in the blocking layer and a portion of the conductive layer, and wherein the trench locates approximately above the contact hole. Finally, an oxide layer is formed on the inner surface of the trench; and the blocking layer and a portion of the conductive layer are etched using the oxide layer as a mask, thereby forming a cylindrical electrode of the capacitor.

摘要翻译： 公开了一种用于形成动态随机存取存储器单元的圆柱形电容器的方法。 该方法包括首先提供其上具有电介质层的半导体衬底，在电介质层中形成的至少一个接触孔，其中接触孔从电介质层的顶表面延伸到衬底的表面。 接下来，在电介质层上形成导电层，并且在导电层上进一步形成阻挡层。 导电层填充接触孔，其中在阻挡层中形成至少一个沟槽和导电层的一部分，并且其中沟槽大致位于接触孔的上方。 最后，在沟槽的内表面上形成氧化物层; 并且使用氧化物层作为掩模来蚀刻阻挡层和导电层的一部分，从而形成电容器的圆柱形电极。