公开(公告)号：US06271088B1

公开(公告)日：2001-08-07

申请号：US09754350

申请日：2001-01-05

申请人： Chih-Cheng Liu ,  De-Yuan Wu

发明人： Chih-Cheng Liu ,  De-Yuan Wu

IPC分类号： H01L218247

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7881

摘要： A method of fabricating a buried vertical split gate memory cell is disclosed. First, a first trench is created in an SOI substrate for accommodating a floating gate. A second trench, having a smaller width than that of the first trench, is then created at the bottom of the first trench for accommodating a word line/control gate. Simultaneously, a silicon sidewall step structure is produced and functions as a vertical channel of the buried vertical split gate memory cell, wherein the vertical control gate channel length (LCG) and the floating gate channel length (LFG) is 0.25 micrometers and about 3.5 nm, respectively.

摘要翻译： 公开了一种制造掩埋垂直分离栅极存储单元的方法。 首先，在用于容纳浮动栅极的SOI衬底中形成第一沟槽。 然后在第一沟槽的底部形成具有比第一沟槽小的宽度的第二沟槽，用于容纳字线/控制门。 同时，产生硅侧壁台阶结构并用作埋入垂直分离栅极存储单元的垂直沟道，其中垂直控制栅极沟道长度（LCG）和浮动栅极沟道长度（LFG）为0.25微米，约3.5nm ， 分别。

公开(公告)号：US06159833A

公开(公告)日：2000-12-12

申请号：US391322

申请日：1999-09-08

申请人： Chin-Hui Lee ,  Chien-Hua Tsai ,  Chih-Cheng Liu

发明人： Chin-Hui Lee ,  Chien-Hua Tsai ,  Chih-Cheng Liu

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/02063 ,  H01L21/31116 ,  H01L21/76802 ,  Y10S438/906

摘要： The present invention provides a method of forming a contact hole in a semiconductor wafer. The semiconductor wafer comprises a silicon substrate, a silicon--oxygen layer positioned on the silicon substrate, and a photoresist layer positioned on the silicon--oxygen layer. An anisotropic dry-etching process is performed to vertically remove the silicon--oxygen layer below the opening to a predetermined depth to form the contact hole which contains a polymer layer on its surface. A soft-etching process is performed to remove the polymer layer in the contact hole. The dry-etching process and soft-etching process are performed alternatively to vertically remove the silicon--oxygen layer under the contact hole until the surface of the silicon substrate can be reached through the contact hole.

摘要翻译： 本发明提供一种在半导体晶片中形成接触孔的方法。 半导体晶片包括硅衬底，位于硅衬底上的硅 - 氧层和位于硅 - 氧层上的光致抗蚀剂层。 进行各向异性干蚀刻工艺以将开口下方的硅 - 氧层垂直移除到预定深度，以形成其表面上含有聚合物层的接触孔。 进行软蚀刻工艺以去除接触孔中的聚合物层。 交替地进行干蚀刻处理和软蚀刻处理，以垂直地去除接触孔下方的硅 - 氧层，直到硅衬底的表面可以通过接触孔到达。

公开(公告)号：US07949437B2

公开(公告)日：2011-05-24

申请号：US11684699

申请日：2007-03-12

申请人： Ching-Chang Wong ,  Chih-Cheng Liu ,  Yang-Han Lee ,  Shih-An Li ,  Hou-Yi Wang

发明人： Ching-Chang Wong ,  Chih-Cheng Liu ,  Yang-Han Lee ,  Shih-An Li ,  Hou-Yi Wang

IPC分类号： B62D7/08

CPC分类号： B60L15/2036 ,  G05D1/0272 ,  Y02T10/645 ,  Y02T10/646 ,  Y02T10/72 ,  Y02T10/7275

摘要： The present invention discloses an omnidirectional movement control system, having a move signal generator for generating a plurality of movement signals based on a plurality of first position signals and a plurality of second position signals, and an omnidirectional movement controller for generating a plurality of pulse width modulation signals and a plurality of motor direction change signals based on the movement signals and a plurality of motor encoding disc signals, and a driving circuit for driving motors to rotate a plurality of omnidirectional wheels based on the pulse width modulation signals and the motor direction change signals, such that a mobile platform can be moved in any direction and rotated in different directions, so as to provide excellent mobility and flexibility to the mobile platform.

摘要翻译： 本发明公开了一种全向运动控制系统，具有移动信号发生器，用于基于多个第一位置信号和多个第二位置信号产生多个运动信号，以及全向运动控制器，用于产生多个脉冲宽度 基于移动信号和多个电动机编码盘信号的调制信号和多个电动机方向改变信号，以及用于驱动电动机的驱动电路，其基于脉宽调制信号和电动机方向变化来驱动多个全向轮的旋转 信号，使得移动平台可以沿任何方向移动并沿不同方向旋转，从而为移动平台提供优异的移动性和灵活性。

公开(公告)号：US20080080245A1

公开(公告)日：2008-04-03

申请号：US11306092

申请日：2005-12-15

申请人： Chih-Cheng Liu

发明人： Chih-Cheng Liu

IPC分类号： G11C11/34 ,  H01L29/788

CPC分类号： H01L29/7923 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/66833

摘要： A P-channel memory is provided. Each memory unit is constructed of a substrate, a gate structure, a first charge trapping layer, a second charge trapping layer, a first source/drain, and a second source/drain. The gate structure is located above the substrate. The first charge trapping layer and the second charge trapping layer are located on both sidewalls of the gate structure for storing two bit of data in a single memory unit. The first source/drain and the second source/drain are located in the substrate on both sides of the gate structure.

摘要翻译： 提供了P通道存储器。 每个存储器单元由衬底，栅极结构，第一电荷俘获层，第二电荷俘获层，第一源极/漏极和第二源极/漏极构成。 栅极结构位于衬底上方。 第一电荷俘获层和第二电荷俘获层位于栅极结构的两个侧壁上，用于将两位数据存储在单个存储器单元中。 第一源极/漏极和第二源极/漏极位于栅极结构两侧的衬底中。

公开(公告)号：US06392924B1

公开(公告)日：2002-05-21

申请号：US09828376

申请日：2001-04-06

申请人： Chih-Cheng Liu ,  Der-Yuan Wu

发明人： Chih-Cheng Liu ,  Der-Yuan Wu

IPC分类号： G11C1100

CPC分类号： H01L27/222 ,  G11C11/15 ,  G11C11/16

摘要： The array includes: a plurality of pseudo spin valve (PSV) cells; a plurality of parallel bit lines, wherein a plurality of bit lines are straight lines and located under the plurality of pseudo spin valve (PSV) cells; a plurality of parallel word lines, wherein a plurality of word lines are continuous-bended lines having a first straight line, a second straight line and a third straight line. These straight lines of the word lines are orthogonal each other, wherein the first straight line and the third straight line are parallel. The first straight line and the third straight line are individually orthogonal with the direction of the bit lines. Furthermore, the second straight lines of the word lines are individually located on the pseudo spin valve (PSV) cells, and the second straight lines are parallel with the direction of the bit lines, so as to increase the magnetresistance ratio.

摘要翻译： 阵列包括：多个假自旋阀（PSV）单元; 多个并行位线，其中多个位线是直线并位于所述多个伪自旋阀（PSV）单元之下; 多个平行字线，其中多个字线是具有第一直线，第二直线和第三直线的连续弯曲线。 字线的这些直线彼此正交，其中第一直线和第三直线平行。 第一直线和第三直线与位线的方向分别正交。 此外，字线的第二直线分别位于伪自旋阀（PSV）单元上，并且第二直线与位线的方向平行，以增加磁阻比。

公开(公告)号：US06221703B1

公开(公告)日：2001-04-24

申请号：US09352749

申请日：1999-07-14

申请人： Chih-Cheng Liu ,  Chin-Hui Lee

发明人： Chih-Cheng Liu ,  Chin-Hui Lee

IPC分类号： H10L21339

CPC分类号： H01L29/1033 ,  H01L21/2652

摘要： The invention relates to an ion implantation method for adjusting the threshold voltage of MOS transistors. The MOS transistor is employed in a DRAM (dynamic random access memory) memory cell in a semiconductor wafer and comprises a substrate, a gate insulating layer positioned on the substrate, and a gate conducting layer with a rectangular-shaped cross section positioned on the gate insulating layer. The method comprises performing an ion implantation process at a predetermined dosage and ion energy to implant dopants through the gate conducting layer and gate insulating layer and deposit the dopants into the superficial portion of the substrate below the gate insulating layer.

摘要翻译： 本发明涉及用于调整MOS晶体管的阈值电压的离子注入方法。 MOS晶体管用于半导体晶片中的DRAM（动态随机存取存储器）存储单元，并且包括基板，位于基板上的栅极绝缘层和位于栅极上的矩形横截面的栅极导电层 绝缘层。 该方法包括以预定剂量和离子能量进行离子注入工艺以通过栅极导电层和栅极绝缘层注入掺杂剂，并将掺杂剂沉积到栅极绝缘层下方的衬底的表面部分中。

公开(公告)号：US20080228328A1

公开(公告)日：2008-09-18

申请号：US11684699

申请日：2007-03-12

申请人： Ching-Chang Wong ,  Chih-Cheng Liu ,  Yang-Han Lee ,  Shih-An Li ,  Hou-Yi Wang

发明人： Ching-Chang Wong ,  Chih-Cheng Liu ,  Yang-Han Lee ,  Shih-An Li ,  Hou-Yi Wang

IPC分类号： G06F17/00

CPC分类号： B60L15/2036 ,  G05D1/0272 ,  Y02T10/645 ,  Y02T10/646 ,  Y02T10/72 ,  Y02T10/7275

摘要： The present invention discloses an omnidirectional movement control system, having a move signal generator for generating a plurality of movement signals based on a plurality of first position signals and a plurality of second position signals, and an omnidirectional movement controller for generating a plurality of pulse width modulation signals and a plurality of motor direction change signals based on the movement signals and a plurality of motor encoding disc signals, and a driving circuit for driving motors to rotate a plurality of omnidirectional wheels based on the pulse width modulation signals and the motor direction change signals, such that a mobile platform can be moved in any direction and rotated in different directions, so as to provide excellent mobility and flexibility to the mobile platform.

摘要翻译： 本发明公开了一种全向运动控制系统，具有移动信号发生器，用于基于多个第一位置信号和多个第二位置信号产生多个运动信号，以及全向运动控制器，用于产生多个脉冲宽度 基于移动信号和多个电动机编码盘信号的调制信号和多个电动机方向改变信号，以及用于驱动电动机的驱动电路，其基于脉宽调制信号和电动机方向变化来驱动多个全向轮的旋转 信号，使得移动平台可以沿任何方向移动并沿不同方向旋转，从而为移动平台提供优异的移动性和灵活性。

公开(公告)号：US07200040B2

公开(公告)日：2007-04-03

申请号：US11162365

申请日：2005-09-08

申请人： Chih-Cheng Liu

发明人： Chih-Cheng Liu

IPC分类号： G11C11/34

CPC分类号： G11C16/0475

摘要： A method of operating a P-channel memory is described. The P-channel memory includes a substrate, a gate formed over the substrate, a charge trapping structure disposed between the substrate and the gate, and the first and second sources/drains formed in the substrate adjacent to two sides of the charge trapping structure. An erasing operation is performed by applying a first voltage to the second source/drain, applying a second voltage to the first source/drain, applying a third voltage to the gate, and applying a forth voltage to the substrate. Hot holes are injected in the charge trapping structure to erase the P-channel memory by the tertiary hot hole mechanism. The absolute value of the voltage differential between the third and the forth voltages is equal to, or less than 6V, and the second voltage is smaller than the third voltage.

摘要翻译： 描述操作P信道存储器的方法。 P沟道存储器包括衬底，形成在衬底上的栅极，设置在衬底和栅极之间的电荷俘获结构以及形成在衬底中的与电荷俘获结构的两侧相邻的第一和第二源极/漏极。 通过向第二源极/漏极施加第一电压，向第一源极/漏极施加第二电压，向栅极施加第三电压，并向衬底施加第四电压来执行擦除操作。 在电荷捕获结构中注入热孔，通过第三热孔机制擦除P沟道存储器。 第三和第四电压之间的电压差的绝对值等于或小于6V，并且第二电压小于第三电压。

公开(公告)号：US20070063218A1

公开(公告)日：2007-03-22

申请号：US11306101

申请日：2005-12-16

申请人： Chih-Cheng Liu

发明人： Chih-Cheng Liu

IPC分类号： H01L29/74

CPC分类号： H01L29/78 ,  H01L27/0266

摘要： A semiconductor device is provided. The semiconductor device is suitable for an electrostatic discharge protection circuit. The semiconductor device includes a gate structure, an N-type source region, an N-type well region, an N-type drain region, and an N-doped region. Wherein, the gate structure comprises a gate and a gate oxide layer. The gate oxide layer is disposed between the gate and a substrate. In addition, the N-type source region is disposed in the substrate at one side of the gate, and the N-type well region is disposed in the substrate at another side of the gate. The N-type drain region is disposed in the substrate between the N-type well region and the gate structure. The N-type drain region has a first toothed part disposed in the N-type well region. The N-doped region is disposed in the N-type well region, and the N-doped region has a second toothed part.

摘要翻译： 提供半导体器件。 该半导体器件适用于静电放电保护电路。 半导体器件包括栅极结构，N型源极区，N型阱区，N型漏极区和N掺杂区。 其中，栅极结构包括栅极和栅极氧化物层。 栅极氧化层设置在栅极和衬底之间。 此外，N型源极区域设置在栅极一侧的衬底中，并且N型阱区域设置在栅极另一侧的衬底中。 N型漏极区域设置在N型阱区域和栅极结构之间的衬底中。 N型漏极区域具有设置在N型阱区域中的第一齿形部分。 N掺杂区域设置在N型阱区域中，并且N掺杂区域具有第二齿形部分。

公开(公告)号：US20060215460A1

公开(公告)日：2006-09-28

申请号：US11162365

申请日：2005-09-08

申请人： Chih-Cheng Liu

发明人： Chih-Cheng Liu

IPC分类号： G11C16/04

CPC分类号： G11C16/0475

摘要： A method of operating a P-channel memory is described. The P-channel memory includes a substrate, a gate formed over the substrate, a charge trapping structure disposed between the substrate and the gate, and the first and second sources/drains formed in the substrate adjacent to two sides of the charge trapping structure. An erasing operation is performed by applying a first voltage to the second source/drain, applying a second voltage to the first source/drain, applying a third voltage to the gate, and applying a forth voltage to the substrate. Hot holes are injected in the charge trapping structure to erase the P-channel memory by the tertiary hot hole mechanism. The absolute value of the voltage differential between the third and the forth voltages is equal to, or less than 6V, and the second voltage is smaller than the third voltage.

摘要翻译： 描述操作P信道存储器的方法。 P沟道存储器包括衬底，形成在衬底上的栅极，设置在衬底和栅极之间的电荷俘获结构以及形成在衬底中的与电荷俘获结构的两侧相邻的第一和第二源极/漏极。 通过向第二源极/漏极施加第一电压，向第一源极/漏极施加第二电压，向栅极施加第三电压，并向衬底施加第四电压来执行擦除操作。 在电荷捕获结构中注入热孔，通过第三热孔机制擦除P沟道存储器。 第三和第四电压之间的电压差的绝对值等于或小于6V，并且第二电压小于第三电压。