公开(公告)号：US20120161813A1

公开(公告)日：2012-06-28

申请号：US13305446

申请日：2011-11-28

Applicant: Han Jin CHO ,  Young Hwan BAE

Inventor： Han Jin CHO ,  Young Hwan BAE

IPC: H03K19/177

CPC classification number: H03K19/17748 ,  H03K19/0008

Abstract: A switch apparatus of a Field Programmable Gate Array (FPGA) includes a pass transistor configured to switch and transfer an input signal to a logic cell according to a value of a configuration memory, and a voltage maintaining unit connected between the configuration memory and a gate of the pass transistor and configured to delay a drop of a gate voltage.

Abstract translation: 现场可编程门阵列（FPGA）的开关装置包括：传输晶体管，被配置为根据配置存储器的值来切换输入信号并将其传送到逻辑单元;以及电压保持单元，连接在配置存储器和门 并且被配置为延迟栅极电压的下降。

公开(公告)号：US20130147516A1

公开(公告)日：2013-06-13

申请号：US13607637

申请日：2012-09-07

Applicant: Han Jin CHO ,  Young Hwan Bae

Inventor： Han Jin CHO ,  Young Hwan Bae

IPC: H03K19/177

CPC classification number: H03K19/17744 ,  H03K19/1737 ,  H03K19/1776

Abstract: A switch block circuit in a field programmable gate array is provided. The switch block circuit includes a configuration memory unit including first group memories and second group memories and a switching unit including first group switching transistors and second group switching transistors. The switch block circuit further includes a selection unit for correspondingly connecting the second group memories with the second group switching transistors depending on an operation mode. The switch block is efficiently reconfigurable depending on the intended use, and configuration memories unused in a specific operation mode may be applied to other purposes.

Abstract translation: 提供现场可编程门阵列中的开关块电路。 开关块电路包括配置存储单元，其包括第一组存储器和第二组存储器，以及包括第一组开关晶体管和第二组开关晶体管的开关单元。 开关块电路还包括用于根据操作模式相应地将第二组存储器与第二组开关晶体管连接的选择单元。 切换块根据预期用途有效地可重新配置，并且在特定操作模式中未使用的配置存储器可以应用于其他目的。

公开(公告)号：US20110149984A1

公开(公告)日：2011-06-23

申请号：US12961752

申请日：2010-12-07

Applicant: Han Jin CHO ,  Young Hwan Bae

Inventor： Han Jin CHO ,  Young Hwan Bae

IPC: H04L12/56 ,  G11C7/10

CPC classification number: H03K19/177

Abstract: Disclosed are a configuration memory apparatus and a router system using the same. The configuration memory apparatus includes: a selection unit selecting one of a first external device and a storage unit and receiving data; a register storing input data received from the selection unit; a storage unit storing data received from the register; and an I/O unit controlling transmission and reception of data to and from the register and a second external device.

Abstract translation: 公开了一种配置存储装置和使用该配置存储装置的路由器系统。 配置存储装置包括：选择单元，选择第一外部设备和存储单元中的一个并接收数据; 存储从所述选择单元接收的输入数据的寄存器; 存储单元，存储从寄存器接收的数据; 以及I / O单元，用于控制向寄存器和从第二外部设备发送和接收数据的I / O单元。

公开(公告)号：US20110309885A1

公开(公告)日：2011-12-22

申请号：US12878476

申请日：2010-09-09

Applicant: Myeung Su KIM ,  Han Jin CHO ,  Joon Hyung LIM ,  Kyung Hee HONG ,  Yong Il KWON

Inventor： Myeung Su KIM ,  Han Jin CHO ,  Joon Hyung LIM ,  Kyung Hee HONG ,  Yong Il KWON

IPC: H03K3/03

CPC classification number: H03K3/0322 ,  H03K3/012

Abstract: Disclosed herein is a delay circuit for a low power ring oscillator. The delay circuit includes: a pair of N type transistors that receive first differential input signals Vin1+ and Vin1−; a pair of P type transistors that receive second differential input signals Vin2+ and Vin2−; a differential output terminal that outputs differential output signals Vout+ and Vout− generated from the pair of N type transistors and the pair of P type transistors; an N type detector that supplies a body voltage to the pair of N type transistors; and a P type detector that supplies a body voltage to the pair of P type transistors.

Abstract translation: 这里公开了一种用于低功率环形振荡器的延迟电路。 延迟电路包括：一对N型晶体管，其接收第一差分输入信号Vin1 +和Vin1-; 一对P型晶体管，接收第二差分输入信号Vin2 +和Vin2-; 差分输出端子，其输出从所述一对N型晶体管和所述一对P型晶体管产生的差分输出信号Vout +和Vout-; N型检测器，其向所述一对N型晶体管提供体电压; 以及向该P型晶体管对提供体电压的P型检测器。

公开(公告)号：US20100142620A1

公开(公告)日：2010-06-10

申请号：US12630827

申请日：2009-12-03

Applicant: Mi Young LEE ,  Han Jin CHO

Inventor： Mi Young LEE ,  Han Jin CHO

IPC: H04N7/26

CPC classification number: H04N19/395 ,  H04N19/51

Abstract: Disclosed is a technique that shifts the position of a motion compensation block by an error of a motion field and then performs motion compensation to estimate a current frame from past and future frames in digital video coding (DVC), thereby enhancing the accuracy of current frame estimation results.

Abstract translation: 公开了一种通过运动场的误差移动运动补偿块的位置，然后进行运动补偿以估计数字视频编码（DVC）中的过去和未来帧的当前帧，从而提高当前帧的精度 估计结果。

公开(公告)号：US20130082672A1

公开(公告)日：2013-04-04

申请号：US13348464

申请日：2012-01-11

Applicant: Myeung Su KIM ,  Joon Hyung LIM ,  Sang Hoon HWANG ,  Sang Hyun MIN ,  Han Jin CHO ,  Tah Joon PARK

Inventor： Myeung Su KIM ,  Joon Hyung LIM ,  Sang Hoon HWANG ,  Sang Hyun MIN ,  Han Jin CHO ,  Tah Joon PARK

IPC: G05F1/10

CPC classification number: G05F1/575

Abstract: There is provided a low drop-out regulator. The low drop-out regulator includes an amplifier including an odd number of operational amplifiers connected to one another in series, and an output unit including a pass transistor operated by an output from the amplifier and generating an output voltage to be applied to a load, wherein the pass transistor is an N-channel transistor, and the amplifier controls a feedback loop gain between an output terminal of one of the odd number of operational amplifiers and the output unit. The feedback loop gain may be controlled independently from the trans-conductance of the pass transistor, whereby the stable output voltage may be generated, even in the case that the load and the input voltage are changed, and the design parameter may be simplified.

Abstract translation: 提供了一个低压差调节器。 低压差调节器包括一个包括串联连接的奇数运算放大器的放大器，以及一个输出单元，包括一个由放大器的输出端工作的通过晶体管，并产生一个要加到负载上的输出电压， 其中所述传输晶体管是N沟道晶体管，并且所述放大器控制所述奇数个运算放大器之一的输出端与所述输出单元之间的反馈环路增益。 反馈环路增益可以独立于传输晶体管的跨导电阻来控制，由此即使在改变负载和输入电压的情况下也可以产生稳定的输出电压，并且可以简化设计参数。

公开(公告)号：US20130107775A1

公开(公告)日：2013-05-02

申请号：US13342676

申请日：2012-01-03

Applicant: Han Jin CHO ,  Jae Hyung Lee ,  Myeung Su Kim ,  Joon Hyung Lim ,  Tah Joon Park

Inventor： Han Jin CHO ,  Jae Hyung Lee ,  Myeung Su Kim ,  Joon Hyung Lim ,  Tah Joon Park

IPC: H04W52/02

CPC classification number: H04W52/0235 ,  Y02D70/166

Abstract: A wireless communications terminal includes: an RF wake-up detection unit detecting a first RF signal including an RF ID for waking up; and a wireless communications unit waking up when the RF ID included in the first RF signal detected by the RF wake-up detection unit matches a pre-set reference ID in a sleep mode.

Abstract translation: 无线通信终端包括：RF唤醒检测单元，检测包括用于唤醒的RF ID的第一RF信号; 以及当由所述RF唤醒检测单元检测到的所述第一RF信号中包含的RF ID与睡眠模式中的预设参考ID匹配时，所述无线通信单元被唤醒。