Flash memory devices having multilayered inter-gate dielectric layers including metal oxide layers and methods of manufacturing the same
    1.
    发明授权
    Flash memory devices having multilayered inter-gate dielectric layers including metal oxide layers and methods of manufacturing the same 失效
    具有包括金属氧化物层的多层栅极间电介质层的闪存器件及其制造方法

    公开(公告)号:US07517750B2

    公开(公告)日:2009-04-14

    申请号:US11383102

    申请日:2006-05-12

    IPC分类号: H01L21/8238

    摘要: Embodiments of the present invention provide methods of manufacturing memory devices including forming floating gate patterns on a semiconductor substrate having active regions thereon, wherein the floating gate patterns cover the active regions and are spaced apart from the active regions; forming an inter-gate dielectric layer on the semiconductor substrate having the floating gate patterns by alternately stacking a zirconium oxide layer and an aluminum oxide layer at least once, wherein the inter-gate dielectric layer is formed by a deposition process using O3 gas as a reactive gas; forming a control gate layer on the inter-gate dielectric layer; and forming a control gate, an inter-gate dielectric layer pattern and a floating gate by sequentially patterning the control gate layer, the inter-gate dielectric layer and the floating gate pattern, wherein the inter-gate dielectric layer pattern and the control gate are sequentially stacked across the active regions, and the floating gate is formed between the active regions and the inter-gate dielectric layer pattern Memory devices, such as flash memory devices are also provided.

    摘要翻译: 本发明的实施例提供了制造存储器件的方法,包括在其上具有有源区的半导体衬底上形成浮置栅极图案,其中浮置栅极图案覆盖有源区并与有源区间隔开; 通过将氧化锆层和氧化铝层交替层叠至少一次来形成具有浮置栅极图案的半导体衬底上的栅极间电介质层,其中栅极间电介质层通过使用O 3气体作为 反应气体 在所述栅极间电介质层上形成控制栅极层; 以及通过对控制栅极层,栅极间电介质层和浮置栅极图案顺序构图来形成控制栅极,栅极间电介质层图案和浮置栅极,其中栅极间电介质层图案和控制栅极是 顺序堆叠在有源区上,并且在有源区之间形成浮栅,并且还提供诸如闪存器件的栅极间电介质层图案存储器件。

    FLASH MEMORY DEVICES HAVING MULTILAYERED INTER-GATE DIELECTRIC LAYERS INCLUDING METAL OXIDE LAYERS AND METHODS OF MANUFACTURING THE SAME
    4.
    发明申请
    FLASH MEMORY DEVICES HAVING MULTILAYERED INTER-GATE DIELECTRIC LAYERS INCLUDING METAL OXIDE LAYERS AND METHODS OF MANUFACTURING THE SAME 失效
    具有包括金属氧化物层的多层间隙介电层的闪存存储器件及其制造方法

    公开(公告)号:US20070026608A1

    公开(公告)日:2007-02-01

    申请号:US11383102

    申请日:2006-05-12

    IPC分类号: H01L21/336

    摘要: Embodiments of the present invention provide methods of manufacturing memory devices including forming floating gate patterns on a semiconductor substrate having active regions thereon, wherein the floating gate patterns cover the active regions and are spaced apart from the active regions; forming an inter-gate dielectric layer on the semiconductor substrate having the floating gate patterns by alternately stacking a zirconium oxide layer and an aluminum oxide layer at least once, wherein the inter-gate dielectric layer is formed by a deposition process using O3 gas as a reactive gas; forming a control gate layer on the inter-gate dielectric layer; and forming a control gate, an inter-gate dielectric layer pattern and a floating gate by sequentially patterning the control gate layer, the inter-gate dielectric layer and the floating gate pattern, wherein the inter-gate dielectric layer pattern and the control gate are sequentially stacked across the active regions, and the floating gate is formed between the active regions and the inter-gate dielectric layer pattern Memory devices, such as flash memory devices are also provided.

    摘要翻译: 本发明的实施例提供了制造存储器件的方法,包括在其上具有有源区的半导体衬底上形成浮置栅极图案,其中浮置栅极图案覆盖有源区并与有源区间隔开; 通过将氧化锆层和氧化铝层交替层叠至少一次来形成具有浮置栅极图案的半导体衬底上的栅极间电介质层,其中栅极间电介质层通过使用O 2的沉积工艺形成, 3气体作为反应气体; 在所述栅极间电介质层上形成控制栅极层; 以及通过对控制栅极层,栅极间电介质层和浮置栅极图案顺序构图来形成控制栅极,栅极间电介质层图案和浮置栅极,其中栅极间电介质层图案和控制栅极是 顺序堆叠在有源区上,并且在有源区之间形成浮栅,并且还提供诸如闪存器件的栅极间电介质层图案存储器件。

    Non-volatile memory device and method of manufacturing the same
    7.
    发明授权
    Non-volatile memory device and method of manufacturing the same 失效
    非易失性存储器件及其制造方法

    公开(公告)号:US07635633B2

    公开(公告)日:2009-12-22

    申请号:US11898039

    申请日:2007-09-07

    IPC分类号: H01L21/336

    摘要: In a non-volatile memory device and a method of manufacturing the non-volatile memory device, a tunnel insulating layer, a charge trapping layer, a dielectric layer and a conductive layer may be sequentially formed on a channel region of a substrate. The conductive layer may be patterned to form a gate electrode and spacers may be formed on sidewalls of the gate electrode. A dielectric layer pattern, a charge trapping layer pattern, and a tunnel insulating layer pattern may be formed on the channel region by an anisotropic etching process using the spacers as an etch mask. Sidewalls of the charge trapping layer pattern may be removed by an isotropic etching process to reduce the width thereof. Thus, the likelihood of lateral diffusion of electrons may be reduced or prevented in the charge trapping layer pattern and high temperature stress characteristics of the non-volatile memory device may be improved.

    摘要翻译: 在非易失性存储器件和制造非易失性存储器件的方法中,隧道绝缘层,电荷俘获层,电介质层和导电层可以顺序形成在衬底的沟道区上。 可以将导电层图案化以形成栅电极,并且可以在栅电极的侧壁上形成间隔物。 可以通过使用间隔物作为蚀刻掩模的各向异性蚀刻工艺在沟道区上形成电介质层图案,电荷俘获层图案和隧道绝缘层图案。 可以通过各向同性蚀刻工艺去除电荷俘获层图案的侧壁以减小其宽度。 因此,电荷捕获层图案中电子的横向扩散的可能性可能会降低或被抑制,并且可以提高非易失性存储器件的高温应力特性。

    Non-volatile memory device and method of manufacturing the same
    8.
    发明申请
    Non-volatile memory device and method of manufacturing the same 失效
    非易失性存储器件及其制造方法

    公开(公告)号:US20080061360A1

    公开(公告)日:2008-03-13

    申请号:US11898039

    申请日:2007-09-07

    IPC分类号: H01L29/792 H01L21/336

    摘要: In a non-volatile memory device and a method of manufacturing the non-volatile memory device, a tunnel insulating layer, a charge trapping layer, a dielectric layer and a conductive layer may be sequentially formed on a channel region of a substrate. The conductive layer may be patterned to form a gate electrode and spacers may be formed on sidewalls of the gate electrode. A dielectric layer pattern, a charge trapping layer pattern, and a tunnel insulating layer pattern may be formed on the channel region by an anisotropic etching process using the spacers as an etch mask. Sidewalls of the charge trapping layer pattern may be removed by an isotropic etching process to reduce the width thereof. Thus, the likelihood of lateral diffusion of electrons may be reduced or prevented in the charge trapping layer pattern and high temperature stress characteristics of the non-volatile memory device may be improved.

    摘要翻译: 在非易失性存储器件和制造非易失性存储器件的方法中,隧道绝缘层,电荷俘获层,电介质层和导电层可以顺序形成在衬底的沟道区上。 可以将导电层图案化以形成栅电极,并且可以在栅电极的侧壁上形成间隔物。 可以通过使用间隔物作为蚀刻掩模的各向异性蚀刻工艺在沟道区上形成电介质层图案,电荷俘获层图案和隧道绝缘层图案。 可以通过各向同性蚀刻工艺去除电荷俘获层图案的侧壁以减小其宽度。 因此,电荷捕获层图案中电子的横向扩散的可能性可能会降低或被抑制,并且可以提高非易失性存储器件的高温应力特性。