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    Thermally assisted dielectric charge trapping flash
    1.
    发明授权
    Thermally assisted dielectric charge trapping flash 有权
    热辅助电介质电荷捕捉闪光

    公开(公告)号：US08488387B2

    公开(公告)日：2013-07-16

    申请号：US13099298

    申请日：2011-05-02

    Applicant: Hang-Ting Lue ,  Chih-Ping Chen ,  Chih-Chang Hsieh ,  Yi-Hsuan Hsiao

    Inventor： Hang-Ting Lue ,  Chih-Ping Chen ,  Chih-Chang Hsieh ,  Yi-Hsuan Hsiao

    IPC: G11C16/04

    CPC classification number: G11C16/349 ,  G11C16/0416 ,  G11C16/0483 ,  H01L29/792

    Abstract: A memory device includes an array of dielectric charge trapping structures memory cells including word lines and bit lines. Control circuitry is coupled to the array arranged to control read, program and erase operations. A controller is arranged with supporting circuitry thermally annealing charge trapping structures in the memory cells in the array. Word line drivers and word line termination circuits can be used to induce current flow on the word lines to induce heat for the annealing. The thermal annealing can be applied interleaved with normal operations for recover from cycling damage. Also, the thermally annealing can be applied during mission functions like erase, to improve performance of the function.

    Abstract translation: 存储器件包括介电电荷俘获结构的阵列，包括字线和位线的存储单元。 控制电路耦合到布置成控制读取，编程和擦除操作的阵列。 控制器布置有支持电路，在阵列中的存储器单元中热退火电荷俘获结构。 字线驱动器和字线终端电路可以用于在字线上感应电流以引起退火的热量。 热退火可以与正常操作交错，以循环损伤恢复。 此外，热退火可以在任务功能（如擦除）中应用，以提高功能的性能。

    METHOD FOR OPERATING A SEMICONDUCTOR STRUCTURE
    2.
    发明申请
    METHOD FOR OPERATING A SEMICONDUCTOR STRUCTURE 审中-公开
    操作半导体结构的方法

    公开(公告)号：US20130003434A1

    公开(公告)日：2013-01-03

    申请号：US13612658

    申请日：2012-09-12

    Applicant: Hang-Ting Lue ,  Chih-Ping Chen

    Inventor： Hang-Ting Lue ,  Chih-Ping Chen

    IPC: G11C5/02

    CPC classification number: H01L27/0688 ,  H01L21/8221 ,  H01L21/823487 ,  H01L27/11578 ,  H01L29/792

    Abstract: A method for operating a semiconductor structure is provided. The semiconductor structure comprises a substrate, a first stacked structure, a dielectric element, a conductive line, a first conductive island and a second conductive island. The first stacked structure is formed on the substrate. The first stacked structure comprises first conductive strips and first insulating strips stacked alternately. The first conductive strips are separated from each other by the first insulating strips. The dielectric element is formed on the first stacked structure. The conductive line is formed on the dielectric element. The first conductive island and the second conductive island on opposite sidewalls of the first stacked structure are separated from each other. The method for operating the semiconductor structure comprises respectively applying a first voltage to the first conductive island and applying a second voltage to the second conductive island.

    Abstract translation: 提供了一种用于操作半导体结构的方法。 半导体结构包括基板，第一堆叠结构，电介质元件，导电线，第一导电岛和第二导电岛。 第一层叠结构形成在基板上。 第一堆叠结构包括交替堆叠的第一导电条和第一绝缘条。 第一导电条通过第一绝缘条彼此分开。 电介质元件形成在第一堆叠结构上。 导电线形成在电介质元件上。 第一层叠结构的相对侧壁上的第一导电岛和第二导电岛彼此分离。 用于操作半导体结构的方法包括分别向第一导电岛施加第一电压并向第二导电岛施加第二电压。

    THERMALLY ASSISTED DIELECTRIC CHARGE TRAPPING FLASH
    3.
    发明申请
    THERMALLY ASSISTED DIELECTRIC CHARGE TRAPPING FLASH 有权
    热辅助电容充电闪光灯

    公开(公告)号：US20120281481A1

    公开(公告)日：2012-11-08

    申请号：US13099298

    申请日：2011-05-02

    Applicant: HANG-TING LUE ,  Chih-Ping Chen ,  Chih-Chang Hsieh ,  Yi-Hsuan Hsiao

    Inventor： HANG-TING LUE ,  Chih-Ping Chen ,  Chih-Chang Hsieh ,  Yi-Hsuan Hsiao

    IPC: G11C16/08 ,  G11C16/04

    CPC classification number: G11C16/349 ,  G11C16/0416 ,  G11C16/0483 ,  H01L29/792

    Abstract: A memory device includes an array of dielectric charge trapping structures memory cells including word lines and bit lines. Control circuitry is coupled to the array arranged to control read, program and erase operations. A controller is arranged with supporting circuitry thermally annealing charge trapping structures in the memory cells in the array. Word line drivers and word line termination circuits can be used to induce current flow on the word lines to induce heat for the annealing. The thermal annealing can be applied interleaved with normal operations for recover from cycling damage. Also, the thermally annealing can be applied during mission functions like erase, to improve performance of the function.

    Abstract translation: 存储器件包括介电电荷俘获结构的阵列，包括字线和位线的存储单元。 控制电路耦合到布置成控制读取，编程和擦除操作的阵列。 控制器布置有支持电路，在阵列中的存储器单元中热退火电荷俘获结构。 字线驱动器和字线终端电路可以用于在字线上感应电流以引起退火的热量。 热退火可以与正常操作交错，以循环损伤恢复。 此外，热退火可以在任务功能（如擦除）中应用，以提高功能的性能。

    Soluble polythiophene derivatives
    5.
    发明授权
    Soluble polythiophene derivatives 有权
    可溶性聚噻吩衍生物

    公开(公告)号：US07754847B2

    公开(公告)日：2010-07-13

    申请号：US12130917

    申请日：2008-05-30

    Applicant: Shu-Hua Chan ,  Teng-Chih Chao ,  Bao-Tsan Ko ,  Chih-Ping Chen ,  Chin-Sheng Lin ,  Yi-Ling Chen

    Inventor： Shu-Hua Chan ,  Teng-Chih Chao ,  Bao-Tsan Ko ,  Chih-Ping Chen ,  Chin-Sheng Lin ,  Yi-Ling Chen

    IPC: C08G75/00

    CPC classification number: C08F128/06 ,  C09B57/00 ,  C09B69/109

    Abstract: The present invention discloses a soluble polythiophene derivative containing highly coplanar repeating units. The coplanar characteristic of the TPT (thiophene-phenylene-thiophene) units improves the degree of intramolecular conjugation and intermolecular π-π interaction. The polythiophene derivative exhibits good carrier mobility and is suitable for use in optoelectronic devices such as organic thin film transistors (OTFTs), organic light-emitting diodes (OLEDs), and organic solar cells (OSCs).

    Abstract translation: 本发明公开了含有高共面重复单元的可溶性聚噻吩衍生物。 TPT（噻吩 - 亚苯基 - 噻吩）单体的共面特性提高了分子内共轭的程度和分子间的结合程度。 相互作用。 聚噻吩衍生物具有良好的载流子迁移率，适用于有机薄膜晶体管（OTFT），有机发光二极管（OLED）和有机太阳能电池（OSC）等光电器件。

    VOLTAGE REGULATOR
    7.
    发明申请
    VOLTAGE REGULATOR 有权
    电压稳压器

    公开(公告)号：US20130049724A1

    公开(公告)日：2013-02-28

    申请号：US13297279

    申请日：2011-11-16

    Applicant: Yu-Pao Kung ,  Chih-Ping Chen

    Inventor： Yu-Pao Kung ,  Chih-Ping Chen

    IPC: G05F1/10

    CPC classification number: G05F1/575

    Abstract: A voltage regulator with a low quiescent current is provided. The voltage regulator includes a pulse voltage generating unit, a first switch unit, a regulating unit and a power output unit. The pulse voltage generating unit receives an input voltage to provide an intermittent signal with a predetermined period, and output a pulse voltage according to the intermittent signal. The first switch unit is turned on according to the intermittent signal. The regulating unit converts the pulse voltage into a continuous voltage. The power output unit receives the continuous voltage to output a voltage power through a power output terminal. And, the power output unit detects an output current of the power output terminal to adjust current drive capability of the power output unit dynamically. Thus, the pulse voltage generating unit consumes power while the intermittent signal is enabled, so as to achieve the power saving effect.

    Abstract translation: 提供具有低静态电流的电压调节器。 电压调节器包括脉冲电压产生单元，第一开关单元，调节单元和功率输出单元。 脉冲电压产生单元接收输入电压以提供具有预定周期的间歇信号，并且根据间歇信号输出脉冲电压。 第一开关单元根据间歇信号接通。 调节单元将脉冲电压转换为连续电压。 电力输出单元接收连续电压，通过电力输出端子输出电压电力。 并且，电力输出单元检测电力输出端子的输出电流，动态地调整电力输出单元的电流驱动能力。 因此，脉冲电压产生单元在间歇信号使能的同时消耗电力，从而达到省电效果。

    HOUSING AND METHOD OF FASTENING ELECTRONIC CARD
    8.
    发明申请
    HOUSING AND METHOD OF FASTENING ELECTRONIC CARD 有权
    电子卡的住房和方法

    公开(公告)号：US20120229996A1

    公开(公告)日：2012-09-13

    申请号：US13413602

    申请日：2012-03-06

    Applicant: Ping-Yu Ko ,  Chih-Ping Chen

    Inventor： Ping-Yu Ko ,  Chih-Ping Chen

    IPC: H05K7/02 ,  H05K13/00

    CPC classification number: G06F1/1633 ,  G06F1/185 ,  Y10T29/49002

    Abstract: A housing is usable for positioning selectively a first electronic card having a first locking hole and a second electronic card having a second locking hole, and includes a base plate, a connector for mating with the selected one of the first and second electronic cards, and a movable element including a lever body that has an end portion connected pivotally to the base plate and a third locking hole opposite to the end portion. The lever body is operable to move the third locking hole between a first position, where the third locking hole is aligned with the first locking hole to cooperatively receive a fastener for fastening one of the first and second electronic cards, and a second position, where the third locking hole is aligned with the second locking hole to cooperatively receive the fastener for fastening the other one of the first and second electronic cards.

    Abstract translation: 壳体可用于选择性地定位具有第一锁定孔的第一电子卡和具有第二锁定孔的第二电子卡，并且包括基板，用于与所选择的第一和第二电子卡配合的连接器，以及 一个可移动元件，包括一个杠杆本体，该杠杆主体具有一个可枢转地连接到底板的端部和与该端部相对的第三个锁定孔。 杠杆体可操作以使第三锁定孔在第一位置和第二位置之间移动，在第一位置，第一锁定孔与第一锁定孔对准，以协作地接收用于紧固第一和第二电子卡中的一个的紧固件， 所述第三锁定孔与所述第二锁定孔对准以协作地接收所述紧固件，用于紧固所述第一和第二电子卡片中的另一个。

    Driving circuit for detecting line short defects
    9.
    发明授权
    Driving circuit for detecting line short defects 有权
    用于检测线路短路缺陷的驱动电路

    公开(公告)号：US08248356B2

    公开(公告)日：2012-08-21

    申请号：US12257407

    申请日：2008-10-24

    Applicant: Chih-Ping Chen

    Inventor： Chih-Ping Chen

    IPC: G09G3/36

    CPC classification number: G09G3/006 ,  G09G3/3677 ,  G09G2330/08 ,  G09G2330/12

    Abstract: For detecting line short defects in a display panel, a driving circuit has a plurality of shift registers, a plurality of diode modules, and at least one power supply. Each shift register has an output port for outputting a driving signal sequentially. The diode modules are coupled to the output ports of the shift registers accordingly. The power supply is coupled to the diode modules and forward biases the diode modules to bypass the shift registers during at least a part of a period of detecting line short defects.

    Abstract translation: 为了检测显示面板中的线路短路缺陷，驱动电路具有多个移位寄存器，多个二极管模块和至少一个电源。 每个移位寄存器具有用于顺序地输出驱动信号的输出端口。 二极管模块相应地耦合到移位寄存器的输出端口。 电源耦合到二极管模块，并且在检测线短缺陷的一段时间的至少一部分期间，二极管模块正向偏置旁路移位寄存器。

    Method and apparatus for debugging applications executed on a software relaxed consistency architecture
    10.
    发明申请
    Method and apparatus for debugging applications executed on a software relaxed consistency architecture 审中-公开
    用于调试在软件轻松一致性架构上执行的应用程序的方法和装置

    公开(公告)号：US20070288907A1

    公开(公告)日：2007-12-13

    申请号：US11434738

    申请日：2006-05-16

    Applicant: Jeffrey V. Olivier ,  Chih-Ping Chen ,  Jay P. Hoeflinger ,  Bevin R. Brett

    Inventor： Jeffrey V. Olivier ,  Chih-Ping Chen ,  Jay P. Hoeflinger ,  Bevin R. Brett

    IPC: G06F9/44

    CPC classification number: G06F11/362

    Abstract: A method for debugging a program includes identifying a thread in an unsafe state during a breakpoint. The thread is allowed to continue execution until it reaches a safe state while preventing other threads from executing. According to one aspect of the invention, the thread is in the unsafe state when the thread is executing code to access sharable memory and the sharable memory is in transition. Other embodiments are described and claimed.

    Abstract translation: 用于调试程序的方法包括在断点期间识别处于不安全状态的线程。 允许线程继续执行，直到达到安全状态，同时阻止其他线程执行。 根据本发明的一个方面，当线程执行代码以访问可共享存储器并且可共享存储器处于转换时，线程处于不安全状态。 描述和要求保护其他实施例。

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