公开(公告)号：US20050083081A1

公开(公告)日：2005-04-21

申请号：US10685863

申请日：2003-10-15

申请人： Hans Jacobson ,  Pradip Bose ,  Alper Buyuktosunoglu ,  Peter Cook ,  Philip Emma ,  Prabhakar Kudva ,  Stanley Schuster

发明人： Hans Jacobson ,  Pradip Bose ,  Alper Buyuktosunoglu ,  Peter Cook ,  Philip Emma ,  Prabhakar Kudva ,  Stanley Schuster

IPC分类号： H03K5/00 ,  H03K17/16 ,  H03K19/00

CPC分类号： H03K19/0016

摘要： Leakage current control devices include a circuit having one or more functions in a data path where the functions are executed in a sequence. Each of the functions has power reduction logic to energize each respective function. A leakage control circuit interacts with the power reduction logic, so that the functions are energized or deenergized in a control sequence such that the functions where the data is resident are energized and at least one of the other functions is not energized.

公开(公告)号：US20060156046A1

公开(公告)日：2006-07-13

申请号：US11376544

申请日：2006-03-14

申请人： Hans Jacobson ,  Prabhakar Kudva ,  Pradip Bose ,  Peter Cook ,  Stanley Schuster

发明人： Hans Jacobson ,  Prabhakar Kudva ,  Pradip Bose ,  Peter Cook ,  Stanley Schuster

IPC分类号： G06F1/26

CPC分类号： G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3275 ,  G06F9/3869 ,  G06F9/3871 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/14

摘要： An integrated circuit including a pipeline and a method of operating the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are individually, and selectively, stalled by a stall signal. For each stage a stall signal, delayed with respect to the stall signal of a downstream stage, is generated and used to select whether the pipeline stage in question is triggered. A data valid signal propagating with valid data adds further selection, such that only stages with valid data are stalled.

公开(公告)号：US20060161795A1

公开(公告)日：2006-07-20

申请号：US11375989

申请日：2006-03-14

申请人： Hans Jacobson ,  Prabhakar Kudva ,  Pradip Bose ,  Peter Cook ,  Stanley Schuster

发明人： Hans Jacobson ,  Prabhakar Kudva ,  Pradip Bose ,  Peter Cook ,  Stanley Schuster

IPC分类号： G06F1/26

CPC分类号： G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3275 ,  G06F9/3869 ,  G06F9/3871 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/14

摘要： An integrated circuit including a pipeline and a method of operating the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are individually, and selectively, stalled by a stall signal. For each stage a stall signal, delayed with respect to the stall signal of a downstream stage, is generated and used to select whether the pipeline stage in question is triggered. A data valid signal propagating with valid data adds further selection, such that only stages with valid data are stalled.

摘要翻译： 一种包括管道的集成电路和操作管道的方法。 流水线的每个阶段由一个或多个触发事件触发，并且由失速信号单独且有选择地停止。 对于每个阶段，产生相对于下游级的失速信号延迟的失速信号，并用于选择是否触发所讨论的流水线级。 用有效数据传播的数据有效信号增加了进一步的选择，使得仅有有效数据的阶段停滞。

公开(公告)号：US20060233024A1

公开(公告)日：2006-10-19

申请号：US11108369

申请日：2005-04-18

申请人： Richard Matick ,  Stanley Schuster

发明人： Richard Matick ,  Stanley Schuster

IPC分类号： G11C7/10

CPC分类号： G11C11/4091 ,  G11C11/4085 ,  G11C11/4097

摘要： A hierarchical DRAM array, DRAM macro and logic chip including the DRAM macro embedded in the logic. DRAM array columns are segmented with a small number (e.g., 2-64) of cells connected to a local bit line (LBL) in each segment. Each LBL drives a sense device that drives a global read bit line (GRBL). When a cell storing a high is selected, the cell drives the LBL high, which turns the sense device on to drive the GRBL low. Segments may be used individually (as a macro) or combined with other segments sharing a common GRBL.

摘要翻译： 分层DRAM阵列，DRAM宏和逻辑芯片，其中包含嵌入逻辑的DRAM宏。 DRAM阵列列以与每个段中的局部位线（LBL）连接的小数目（例如，2-64）分段。 每个LBL驱动驱动全局读取位线（GRBL）的检测器件。 当选择存储高电平的单元时，单元驱动LBL为高电平，使开启感测器件以驱动GRBL为低电平。 分段可以单独使用（作为宏）或与共享共同GRBL的其他段组合使用。

公开(公告)号：US20080016277A1

公开(公告)日：2008-01-17

申请号：US11775717

申请日：2007-07-10

申请人： Richard Matick ,  Stanley Schuster

发明人： Richard Matick ,  Stanley Schuster

IPC分类号： G06F12/00

CPC分类号： G11C11/4091 ,  G11C11/4085 ,  G11C11/4097

摘要： A hierarchical DRAM array, DRAM macro and logic chip including the DRAM macro embedded in the logic. DRAM array columns are segmented with a small number (e.g., 2-64) of cells connected to a local bit line (LBL) in each segment. Each LBL drives a sense device that drives a global read bit line (GRBL). When a cell storing a high is selected, the cell drives the LBL high, which turns the sense device on to drive the GRBL low. Segments may be used individually (as a macro) or combined with other segments sharing a common GRBL.

摘要翻译： 分层DRAM阵列，DRAM宏和逻辑芯片，其中包含嵌入逻辑的DRAM宏。 DRAM阵列列以与每个段中的局部位线（LBL）连接的小数目（例如，2-64）分段。 每个LBL驱动驱动全局读取位线（GRBL）的检测器件。 当选择存储高电平的单元时，单元驱动LBL为高电平，使开启感测器件以驱动GRBL为低电平。 分段可以单独使用（作为宏）或与共享共同GRBL的其他段组合使用。