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    INTERLOCKED SYNCHRONOUS PIPELINE CLOCK GATING
    1.
    发明申请
    INTERLOCKED SYNCHRONOUS PIPELINE CLOCK GATING 失效
    互锁同步管道时钟增益

    公开(公告)号：US20070294548A1

    公开(公告)日：2007-12-20

    申请号：US11846847

    申请日：2007-08-29

    申请人： Hans JACOBSON ,  Prabhakar Kudva ,  Pradip Bose ,  Peter COOK ,  Stanley SCHUSTER

    发明人： Hans JACOBSON ,  Prabhakar Kudva ,  Pradip Bose ,  Peter COOK ,  Stanley SCHUSTER

    IPC分类号： G06F1/26

    CPC分类号： G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3275 ,  G06F9/3869 ,  G06F9/3871 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/14

    摘要： An integrated circuit including a pipeline and a method of operating the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are individually, and selectively, stalled by a stall signal. For each stage a stall signal, delayed with respect to the stall signal of a downstream stage, is generated and used to select whether the pipeline stage in question is triggered. A data valid signal propagating with valid data adds further selection, such that only stages with valid data are stalled.

    摘要翻译： 一种包括管道的集成电路和操作管道的方法。 流水线的每个阶段由一个或多个触发事件触发，并且由失速信号单独且有选择地停止。 对于每个阶段，产生相对于下游级的失速信号延迟的失速信号，并用于选择是否触发所讨论的流水线级。 用有效数据传播的数据有效信号增加了进一步的选择，使得仅有有效数据的阶段停滞。

    Interlocked synchronous pipeline clock gating
    3.
    发明申请
    Interlocked synchronous pipeline clock gating 有权
    联锁同步管道时钟门控

    公开(公告)号：US20060161795A1

    公开(公告)日：2006-07-20

    申请号：US11375989

    申请日：2006-03-14

    申请人： Hans Jacobson ,  Prabhakar Kudva ,  Pradip Bose ,  Peter Cook ,  Stanley Schuster

    发明人： Hans Jacobson ,  Prabhakar Kudva ,  Pradip Bose ,  Peter Cook ,  Stanley Schuster

    IPC分类号： G06F1/26

    CPC分类号： G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3275 ,  G06F9/3869 ,  G06F9/3871 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/14

    摘要： An integrated circuit including a pipeline and a method of operating the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are individually, and selectively, stalled by a stall signal. For each stage a stall signal, delayed with respect to the stall signal of a downstream stage, is generated and used to select whether the pipeline stage in question is triggered. A data valid signal propagating with valid data adds further selection, such that only stages with valid data are stalled.

    摘要翻译： 一种包括管道的集成电路和操作管道的方法。 流水线的每个阶段由一个或多个触发事件触发，并且由失速信号单独且有选择地停止。 对于每个阶段，产生相对于下游级的失速信号延迟的失速信号，并用于选择是否触发所讨论的流水线级。 用有效数据传播的数据有效信号增加了进一步的选择，使得仅有有效数据的阶段停滞。

    Method and system for controlling power in a chip through a power-performance monitor and control unit
    5.
    发明申请
    Method and system for controlling power in a chip through a power-performance monitor and control unit 有权
    通过功率监控和控制单元控制芯片功率的方法和系统

    公开(公告)号：US20070198863A1

    公开(公告)日：2007-08-23

    申请号：US11357612

    申请日：2006-02-17

    申请人： Pradip Bose ,  Alper Buyuktosunoglu ,  Chen-Yong Cher ,  Prabhakar Kudva

    发明人： Pradip Bose ,  Alper Buyuktosunoglu ,  Chen-Yong Cher ,  Prabhakar Kudva

    IPC分类号： G06F1/00

    CPC分类号： G06F1/206 ,  G06F1/3203 ,  Y02D10/16

    摘要： A system and method for controlling power and performance in a microprocessor system includes a monitoring and control system integrated into a microprocessor system. The monitoring and control system includes a hierarchical architecture having a plurality of layers. Each layer in the hierarchal architecture is responsive to commands from a higher level, and the commands provide instructions on operations and power distribution, such that the higher levels provide modes of operation and budgets to lower levels and the lower levels provide feedback to the higher levels to control and manage power usage in the microprocessor system both globally and locally.

    摘要翻译： 用于控制微处理器系统中的功率和性能的系统和方法包括集成到微处理器系统中的监视和控制系统。 监视和控制系统包括具有多个层的层次结构。 层次结构中的每层都响应来自更高级别的命令，并且命令提供关于操作和功率分配的指令，使得较高级别提供操作模式和预算以降低级别，并且较低级别向较高级别提供反馈 在全球和本地控制和管理微处理器系统中的电力使用。

    System and method for topology selection to minimize leakage power during synthesis
    6.
    发明申请
    System and method for topology selection to minimize leakage power during synthesis 失效
    用于拓扑选择的系统和方法，以最大限度地减少合成期间的泄漏功率

    公开(公告)号：US20050125761A1

    公开(公告)日：2005-06-09

    申请号：US10731840

    申请日：2003-12-09

    申请人： Hans Jacobson ,  Prabhakar Kudva ,  Leon Sigal

    发明人： Hans Jacobson ,  Prabhakar Kudva ,  Leon Sigal

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505

    摘要： A system for topology selection to minimize leakage power during synthesis, wherein the system is configured to receive a circuit model that has one or more circuit gates. The system is further configured to receive a library having one or more logic gates, wherein each logic gate has a topology and the leakage sensitivities for each of the topologies is calculated. The system is then configured to synthesize a new circuit model by selecting one or more of the topologies based on its leakage sensitivities, wherein the new circuit model has reduced current leakage.

    摘要翻译： 一种用于在合成期间最小化泄漏功率的拓扑选择的系统，其中所述系统被配置为接收具有一个或多个电路门的电路模型。 该系统还被配置为接收具有一个或多个逻辑门的库，其中每个逻辑门具有拓扑，并且计算每个拓扑的泄漏灵敏度。 然后，该系统被配置为通过基于其泄漏灵敏度选择一个或多个拓扑来合成新的电路模型，其中新的电路模型具有减少的电流泄漏。

    Timing closure methodology including placement with initial delay values
    7.
    发明授权
    Timing closure methodology including placement with initial delay values 有权
    定时关闭方法，包括具有初始延迟值的位置

    公开(公告)号：US08621403B2

    公开(公告)日：2013-12-31

    申请号：US10828547

    申请日：2004-04-19

    申请人： Lukas P. P. P. van Ginneken ,  Prabhakar Kudva

    发明人： Lukas P. P. P. van Ginneken ,  Prabhakar Kudva

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072 ,  G06F17/505 ,  G06F17/5068

    摘要： An automated method for designing an integrated circuit layout using a computer based upon an electronic circuit description and based upon cells which are selected from a cell library, each of the cells having an associated area, comprising the steps of: (a) placing each of the cells in the integrated circuit layout so that the cells can be coupled together by wires to form a circuit path having an associated predetermined delay constraint wherein the cells are coupled together based upon the electronic circuit description input to the computer; (b) connecting the cells together with the wires to form the circuit path; and (c) adjusting an area of at least one of the cells to satisfy the associated predetermined delay constraint of the circuit path.

    摘要翻译： 一种用于基于电子电路描述使用计算机设计集成电路布局的自动化方法，并且基于从单元库中选择的单元，其中每个单元具有相关联的区域，包括以下步骤：（a）将每个 集成电路布局中的单元，使得单元可以通过导线耦合在一起以形成具有相关联的预定延迟约束的电路路径，其中基于输入到计算机的电子电路描述将单元耦合在一起; （b）将电池与电线连接以形成电路路径; 以及（c）调整所述单元中的至少一个的区域以满足所述电路路径的相关联的预定延迟约束。

    Method for performing timing closure on VLSI chips in a distributed environment
    8.
    发明授权
    Method for performing timing closure on VLSI chips in a distributed environment 失效
    在分布式环境中对VLSI芯片进行定时关闭的方法

    公开(公告)号：US07178120B2

    公开(公告)日：2007-02-13

    申请号：US10338929

    申请日：2003-01-08

    申请人： Nathaniel Hieter ,  David J. Hathaway ,  Prabhakar Kudva ,  David S. Kung ,  Leon Stok

    发明人： Nathaniel Hieter ,  David J. Hathaway ,  Prabhakar Kudva ,  David S. Kung ,  Leon Stok

    IPC分类号： G06H17/50 ,  G06H9/45

    CPC分类号： G06F17/505 ,  G06F17/5072

    摘要： A method for performing timing closure on VLSI chips in a distributed environment is described. Abstracting the physical and timing resources of a chip and providing an asynchronous method of updating that abstraction allows multiple partitions of a chip to be optimized concurrently. A global view of physical and timing resources is supplied to local optimizations which are applied concurrently to achieve timing closure. Portions of the hierarchy are optimized in separate processes. Partitioning of the chip is performed along hierarchical lines, with each process owning a single partition in the hierarchy. The processes may be executed by a single computer, or spread across multiple computers in a local network. While optimizations performed by a single process are only applied to its given portion of the hierarchy, decisions are made in the context of the entire hierarchy. These optimizations include placement, synthesis, and routing. The present method can also be expanded to include other resources, such as routing resource, power supply current, power/thermal budget, substrate noise budget, and the like, all of which being able to be similarly abstracted and shared.

    摘要翻译： 描述了在分布式环境中对VLSI芯片执行定时闭合的方法。 提取芯片的物理和定时资源并提供更新抽象的异步方法，可以同时优化芯片的多个分区。 将物理和时序资源的全局视图提供给同时实现时序收敛的局部优化。 层次结构的部分在单独的进程中进行了优化。 芯片的分区按照层次线执行，每个进程在层次结构中拥有单个分区。 这些过程可以由单个计算机执行，或者分布在本地网络中的多个计算机上。 虽然单个进程执行的优化仅适用于其给定的层次结构部分，但是在整个层次结构的上下文中进行决策。 这些优化包括放置，合成和路由。 本方法还可以扩展到包括路由资源，电源电流，功率/热预算，衬底噪声预算等其他资源，所有这些资源都能被类似地抽象和共享。

    Method for optimization of logic circuits for routability
    9.
    发明申请
    Method for optimization of logic circuits for routability 失效
    用于优化可布线性逻辑电路的方法

    公开(公告)号：US20050183046A1

    公开(公告)日：2005-08-18

    申请号：US10780140

    申请日：2004-02-17

    申请人： William Dougherty ,  Victor Kravets ,  Prabhakar Kudva ,  Andrew Sullivan

    发明人： William Dougherty ,  Victor Kravets ,  Prabhakar Kudva ,  Andrew Sullivan

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505

    摘要： Routability (or wiring congestion) in a VLSI chip is becoming increasingly important as chip complexity increases. Congestion has a significant impact on performance, yield, and chip area. The present invention targets the optimization of congestion early in technology independent synthesis prior to physical design. Instead of attempting to optimize the logic structure as well as the spatial placement of a circuit, we pose a more modest goal limiting such optimization to the scope of logic synthesis. That is, we propose an aggressive optimization approach that is cognizant of circuit structure during technology independent synthesis and produces more predictable implementations which give better routability and yield.

    摘要翻译： 随着芯片复杂度的增加，VLSI芯片的可路由性（或布线拥塞）变得越来越重要。 拥塞对性能，产量和芯片面积有重大影响。 本发明在物理设计之前针对技术独立综合早期拥塞的优化。 我们不是试图优化逻辑结构以及电路的空间布局，而是将这样的优化限制在逻辑综合的范围之内。 也就是说，我们提出了一种积极的优化方法，在技术独立合成中识别电路结构，并产生更可预测的实现，从而提供更好的可路由性和产量。

    Cross point switch using phase change material
    10.
    发明授权
    Cross point switch using phase change material 有权
    交点开关采用相变材料

    公开(公告)号：US07880194B2

    公开(公告)日：2011-02-01

    申请号：US12106539

    申请日：2008-04-21

    申请人： Matthew J. Breitwisch ,  Chung H. Lam ,  Prabhakar Kudva

    发明人： Matthew J. Breitwisch ,  Chung H. Lam ,  Prabhakar Kudva

    IPC分类号： H01L29/66

    CPC分类号： H03K19/173

    摘要： A cross-point switch and cross-point switch fabric utilizing phase change material, and method of operating the same. The cross-point switch includes a phase change cross-point circuit containing a plurality of terminal nodes connected to a central node. The connections between the terminal nodes and the central nodes are regulated by phase change switches comprised of a phase change material. The phase change switches being controlled by heating elements capable of melting or crystallizing the phase change material in the phase change switch. The heating elements are operated by a separate heating circuit. Each individual heating element is regulated by an individual transistor.

    摘要翻译： 使用相变材料的交叉点开关和交叉点开关织物及其操作方法。 交叉点开关包括包含连接到中央节点的多个终端节点的相变交叉点电路。 终端节点和中心节点之间的连接由相变材料组成的相变开关来调节。 相变开关由能够在相变开关中熔化或结晶相变材料的加热元件控制。 加热元件由单独的加热回路操作。 每个单独的加热元件由单个晶体管调节。