摘要:
A method for manufacturing unsupported metal lattice structures, such as nickel lattices for use as micro-flow sensors in gas analysis devices, employs the steps of two-sided vacuum metallization on a substrate, several photoresist steps, an electroplating step, and an etching step. A number of units can be produced by this method on a single substrate.
摘要:
A process for producing a thin metal structure with a self-supporting frame, such as a grid, characterized by forming a galvanic resistant coating on a first surface of a carrier member with the coating exposing portions of the first surface adjacent the end of the carrier member and portions of the first surface in the configuration of the metal structure to be formed, depositing a layer of metal on the exposed portion of the first surface, removing the galvanic resistant coating, applying an etch resistant coating on the edges of thecarrier member and at least a portion of a second surface adjacent the edges of the carrier member and then selectively etching the carrier member to remove the carrier member except for that portion protected by the etch resistant coating to form the thin metal structure mounted on a self-supporting frame. The carrier member may either be a single member or a multi-layer member which has a metal coating forming the first surface. The process when using a multi-layer includes providing a protective layer on the metal structure and etching away the majority of the carrier member and then subsequently etching the metallic layer and protective layer to produce the metal structure on the frame.
摘要:
MRAM memory having a memory cell array (2) comprising magnetoresistive memory components (6a, 6b) arranged in at least one memory cell layer above a semiconductor substrate (4), word lines (7) and bit lines (8, 9) for making contact with the magnetoresistive memory components (6a, 6b) in the memory cell array (2); and having a drive logic arrangement (5a, 5b, 5c) for driving the magnetoresistive memory components (6a, 6b) in the memory cell array (2) via the word and bit lines (7, 8, 9), the drive logic arrangement (5a, 5b, 5c) being integrated below the memory cell array (2) in and on the semiconductor substrate (4).