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1.发明申请METHOD, APPARATUS, SYSTEM FOR INCLUDING INTERRUPT FUNCTIONALITY IN SENSOR INTERCONNECTS 审中-公开方法，装置，传感器互连中的中断功能系统公开(公告)号：US20140229644A1
公开(公告)日：2014-08-14
申请号：US14178264
申请日：2014-02-11
IPC分类号： G06F13/24 , G06F13/364
CPC分类号： G06F13/364 , G06F13/1673 , G06F13/24 , G06F13/4282 , H04L63/0492
摘要： Methods, apparati, systems for including interrupt functionality in sensor interconnects field are disclosed in the present disclosure. A System on a Chip (SOC) consistent with the present disclosure includes a host and a unified sensor interconnect. A unified sensor interconnect is to be coupled to the host and at least one device. In one or more implementations, the unified sensor interconnect includes a clock line, data line, ground line, and power source line. Further, the unified sensor interconnect is to enable interrupts from at least one of the host or the at least one device.
摘要翻译： 在本公开中公开了用于在传感器互连领域中包括中断功能的方法，装置。 与本公开一致的片上系统（SOC）包括主机和统一的传感器互连。 统一的传感器互连将耦合到主机和至少一个设备。 在一个或多个实现中，统一传感器互连包括时钟线，数据线，接地线和电源线。 此外，统一传感器互连是为了允许来自主机或至少一个设备中的至少一个的中断。
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公开(公告)号：US08867683B2
公开(公告)日：2014-10-21
申请号：US11340438
申请日：2006-01-27
申请人： Haran Thanigasalam
发明人： Haran Thanigasalam
摘要： A receiver for receiving a stream of symbols clocked at a first rate, and providing the symbols at a second clock rate uses two buffers. Incoming symbols are written to a first dual clock buffer at the first rate, and read from the first and second buffer, at the second rate. Underflow of the first buffer is signaled to the second buffer, thereby avoiding the need to insert defined clock compensation symbols at the second rate. Symbols received at the second buffer while underflow is signaled may be ignored. Conveniently, the second buffer may also be used to align symbol data across multiple symbol streams using periodic alignment symbols. An exemplary embodiment conforms to the PCI Express standard.
摘要翻译： 用于接收以第一速率计时的符号流并以第二时钟速率提供符号的接收器使用两个缓冲器。 以第一速率将传入符号写入第一双时钟缓冲器，并以第二速率从第一和第二缓冲器读取。 将第一缓冲器的下溢信号通知给第二缓冲器，从而避免需要以第二速率插入定义的时钟补偿符号。 在下溢期间在第二缓冲器处接收到的符号可以被忽略。 方便地，第二缓冲器还可以用于使用周期性对准符号在多个符号流之间对齐符号数据。 示例性实施例符合PCI Express标准。
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公开(公告)号：US20070177701A1
公开(公告)日：2007-08-02
申请号：US11340438
申请日：2006-01-27
申请人： Haran Thanigasalam
发明人： Haran Thanigasalam
IPC分类号： H04L7/00
摘要： A receiver for receiving a stream of symbols clocked at a first rate, and providing the symbols at a second clock rate uses two buffers. Incoming symbols are written to a first dual clock buffer at the first rate, and read from the first and second buffer, at the second rate. Underflow of the first buffer is signaled to the second buffer, thereby avoiding the need to insert defined clock compensation symbols at the second rate. Symbols received at the second buffer while underflow is signaled may be ignored. Conveniently, the second buffer may also be used to align symbol data across multiple symbol streams using periodic alignment symbols. An exemplary embodiment conforms to the PCI Express standard.
摘要翻译： 用于接收以第一速率计时的符号流并以第二时钟速率提供符号的接收器使用两个缓冲器。 以第一速率将传入符号写入第一双时钟缓冲器，并以第二速率从第一和第二缓冲器读取。 将第一缓冲器的下溢信号通知给第二缓冲器，从而避免需要以第二速率插入定义的时钟补偿符号。 在下溢期间在第二缓冲器处接收到的符号可以被忽略。 方便地，第二缓冲器还可以用于使用周期性对准符号在多个符号流之间对齐符号数据。 示例性实施例符合PCI Express标准。
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