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1.发明授权公开(公告)号：US08338061B2
公开(公告)日：2012-12-25
申请号：US13158234
申请日：2011-06-10
IPC分类号： G03F1/00
摘要： Fluorine-passivated reticles for use in lithography and methods for fabricating and using such reticles are provided. According to one embodiment, a method for performing photolithography comprises placing a fluorine-passivated reticle between an illumination source and a target semiconductor wafer and causing electromagnetic radiation to pass from the illumination source through the fluorine-passivated reticle to the target semiconductor wafer. In another embodiment, a fluorine-passivated reticle comprises a substrate and a patterned fluorine-passivated absorber material layer overlying the substrate. According to another embodiment, a method for fabricating a reticle for use in photolithography comprises providing a substrate and forming a fluorine-passivated absorber material layer overlying the substrate.
摘要翻译： 提供用于光刻的氟钝化的掩模版以及制造和使用这种掩模版的方法。 根据一个实施例，一种用于执行光刻的方法包括在照明源和目标半导体晶片之间放置氟钝化的掩模版，并使电磁辐射从照明源通过氟钝化掩模版到达目标半导体晶片。 在另一个实施例中，氟钝化的掩模版包括衬底和覆盖衬底的图案化的氟钝化吸收材料层。 根据另一实施例，一种用于光刻中使用的掩模版的制造方法包括提供基板并形成覆盖在基板上的氟钝化的吸收材料层。
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2.发明申请公开(公告)号：US20110244377A1
公开(公告)日：2011-10-06
申请号：US13158234
申请日：2011-06-10
IPC分类号： G03F1/14
摘要： Fluorine-passivated reticles for use in lithography and methods for fabricating and using such reticles are provided. According to one embodiment, a method for performing photolithography comprises placing a fluorine-passivated reticle between an illumination source and a target semiconductor wafer and causing electromagnetic radiation to pass from the illumination source through the fluorine-passivated reticle to the target semiconductor wafer. In another embodiment, a fluorine-passivated reticle comprises a substrate and a patterned fluorine-passivated absorber material layer overlying the substrate. According to another embodiment, a method for fabricating a reticle for use in photolithography comprises providing a substrate and forming a fluorine-passivated absorber material layer overlying the substrate.
摘要翻译： 提供用于光刻的氟钝化的掩模版以及制造和使用这种掩模版的方法。 根据一个实施例，一种用于执行光刻的方法包括在照明源和目标半导体晶片之间放置氟钝化的掩模版，并使电磁辐射从照明源通过氟钝化掩模版到达目标半导体晶片。 在另一个实施例中，氟钝化的掩模版包括衬底和覆盖衬底的图案化的氟钝化吸收材料层。 根据另一实施例，一种用于光刻中使用的掩模版的制造方法包括提供基板并形成覆盖在基板上的氟钝化的吸收材料层。
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3.发明授权公开(公告)号：US07985513B2
公开(公告)日：2011-07-26
申请号：US12050383
申请日：2008-03-18
IPC分类号： G03F1/00
摘要： Fluorine-passivated reticles for use in lithography and methods for fabricating and using such reticles are provided. According to one embodiment, a method for performing photolithography comprises placing a fluorine-passivated reticle between an illumination source and a target semiconductor wafer and causing electromagnetic radiation to pass from the illumination source through the fluorine-passivated reticle to the target semiconductor wafer. In another embodiment, a fluorine-passivated reticle comprises a substrate and a patterned fluorine-passivated absorber material layer overlying the substrate. According to another embodiment, a method for fabricating a reticle for use in photolithography comprises providing a substrate and forming a fluorine-passivated absorber material layer overlying the substrate.
摘要翻译： 提供用于光刻的氟钝化的掩模版以及制造和使用这种掩模版的方法。 根据一个实施例，一种用于执行光刻的方法包括在照明源和目标半导体晶片之间放置氟钝化的掩模版，并使电磁辐射从照明源通过氟钝化掩模版到达目标半导体晶片。 在另一个实施例中，氟钝化的掩模版包括衬底和覆盖衬底的图案化的氟钝化吸收材料层。 根据另一实施例，一种用于光刻中使用的掩模版的制造方法包括提供基板并形成覆盖在基板上的氟钝化的吸收材料层。
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公开(公告)号：US20080198453A1
公开(公告)日：2008-08-21
申请号：US11709718
申请日：2007-02-21
IPC分类号： G02B5/30
CPC分类号： G02B5/3058 , G02B5/3075 , G02F1/0136 , G03F7/70566
摘要： According to one exemplary embodiment, an optical polarizer positioned before a light source for use in semiconductor wafer lithography includes an array of aligned nanotubes. The array of aligned nanotubes cause light emitted from the light source and incident on the array of aligned nanotubes to be converted into polarized light for use in the semiconductor wafer lithography. The amount of polarization can be controlled by a voltage source coupled to the array of aligned nanotubes. Chromogenic material of a light filtering layer can vary the wavelength of the polarized light transmitted through the array of aligned nanotubes.
摘要翻译： 根据一个示例性实施例，定位在用于半导体晶片光刻的光源之前的光学偏振器包括排列的纳米管阵列。 排列的纳米管的阵列引起从光源发射并入射到排列的纳米管阵列上的光，以转换为偏光，用于半导体晶片光刻。 极化量可以通过耦合到排列的纳米管阵列的电压源来控制。 光过滤层的显色材料可以改变通过排列的纳米管阵列传输的偏振光的波长。
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公开(公告)号：US08792161B2
公开(公告)日：2014-07-29
申请号：US11709718
申请日：2007-02-21
IPC分类号： G02B5/30
CPC分类号： G02B5/3058 , G02B5/3075 , G02F1/0136 , G03F7/70566
摘要： An optical polarizer positioned before a light source for use in semiconductor wafer lithography including an array of aligned nanotubes. The array of aligned nanotubes cause light emitted from the light source and incident on the array of aligned nanotubes to be converted into polarized light for use in the semiconductor wafer lithography. The amount of polarization can be controlled by a voltage source coupled to the array of aligned nanotubes. Chromogenic material of a light filtering layer can vary the wavelength of the polarized light transmitted through the array of aligned nanotubes.
摘要翻译： 位于用于半导体晶片光刻的光源之前的光学偏振器，包括排列的纳米管阵列。 排列的纳米管的阵列引起从光源发射并入射到排列的纳米管阵列上的光，以转换为偏光，用于半导体晶片光刻。 极化量可以通过耦合到排列的纳米管阵列的电压源来控制。 光过滤层的显色材料可以改变通过排列的纳米管阵列传输的偏振光的波长。
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6.发明授权Method for forming a high resolution resist pattern on a semiconductor wafer 有权在半导体晶片上形成高分辨率抗蚀剂图案的方法公开(公告)号：US08586269B2
公开(公告)日：2013-11-19
申请号：US11726433
申请日：2007-03-22
IPC分类号： G11B11/105
CPC分类号： G03F7/38
摘要： In one disclosed embodiment, a method for forming a high resolution resist pattern on a semiconductor wafer involves forming a layer of resist comprising, for example a polymer matrix and a catalytic species, over a material layer formed over a semiconductor wafer; exposing the layer of resist to patterned radiation; and applying a magnetic field to the semiconductor wafer during a post exposure bake process. In one embodiment, the patterned radiation is provided by an extreme ultraviolet (EUV) light source. In other embodiments, the source of patterned radiation can be an electron beam, or ion beam, for example. In one embodiment, the polymer matrix is an organic polymer matrix such as, for example, styrene, acrylate, or methacrylate. In one embodiment, the catalytic species can be, for example, an acid, a base, or an oxidizing agent.
摘要翻译： 在一个公开的实施例中，在半导体晶片上形成高分辨率抗蚀剂图案的方法包括在半导体晶片上形成的材料层上形成包含例如聚合物基质和催化物质的抗蚀剂层; 将抗蚀剂层暴露于图案化辐射; 以及在后曝光烘烤处理期间向半导体晶片施加磁场。 在一个实施例中，图案化的辐射由极紫外（EUV）光源提供。 在其它实施例中，图案化辐射源可以是例如电子束或离子束。 在一个实施方案中，聚合物基质是有机聚合物基质，例如苯乙烯，丙烯酸酯或甲基丙烯酸酯。 在一个实施方案中，催化物质可以是例如酸，碱或氧化剂。
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公开(公告)号：US06716571B2
公开(公告)日：2004-04-06
申请号：US09819343
申请日：2001-03-28
IPC分类号： G03F700
CPC分类号： H01L21/28123 , Y10S430/143
摘要： A process for forming sub-lithographic features in an integrated circuit is disclosed herein. The process includes modifying a photoresist layer after patterning and development but before it is utilized to pattern the underlying layers. The modified photoresist layer has different etch rates in the vertical and horizontal directions. The modified photoresist layer is trimmed with a plasma etch. A feature included in the trimmed photoresist layer has a sub-lithographic lateral dimension.
摘要翻译： 本文公开了在集成电路中形成次光刻特征的工艺。 该方法包括在图案化和显影之后但在其用于对下面的层进行图案化之前修饰光致抗蚀剂层。 改性光致抗蚀剂层在垂直和水平方向具有不同的蚀刻速率。 用等离子体蚀刻修整修饰的光致抗蚀剂层。 修整的光致抗蚀剂层中包括的特征具有亚光刻横向尺寸。
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8.发明申请Method for forming a high resolution resist pattern on a semiconductor wafer 有权在半导体晶片上形成高分辨率抗蚀剂图案的方法公开(公告)号：US20080233494A1
公开(公告)日：2008-09-25
申请号：US11726433
申请日：2007-03-22
IPC分类号： G03C11/00
CPC分类号： G03F7/38
摘要： In one disclosed embodiment, a method for forming a high resolution resist pattern on a semiconductor wafer involves forming a layer of resist comprising, for example a polymer matrix and a catalytic species, over a material layer formed over a semiconductor wafer; exposing the layer of resist to patterned radiation; and applying a magnetic field to the semiconductor wafer during a post exposure bake process. In one embodiment, the patterned radiation is provided by an extreme ultraviolet (EUV) light source. In other embodiments, the source of patterned radiation can be an electron beam, or ion beam, for example. In one embodiment, the polymer matrix is an organic polymer matrix such as, for example, styrene, acrylate, or methacrylate. In one embodiment, the catalytic species can be, for example, an acid, a base, or an oxidizing agent.
摘要翻译： 在一个公开的实施例中，在半导体晶片上形成高分辨率抗蚀剂图案的方法包括在半导体晶片上形成的材料层上形成包含例如聚合物基质和催化物质的抗蚀剂层; 将抗蚀剂层暴露于图案化辐射; 以及在后曝光烘烤处理期间向半导体晶片施加磁场。 在一个实施例中，图案化的辐射由极紫外（EUV）光源提供。 在其它实施例中，图案化辐射源可以是例如电子束或离子束。 在一个实施方案中，聚合物基质是有机聚合物基质，例如苯乙烯，丙烯酸酯或甲基丙烯酸酯。 在一个实施方案中，催化物质可以是例如酸，碱或氧化剂。
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公开(公告)号：US06787458B1
公开(公告)日：2004-09-07
申请号：US10614397
申请日：2003-07-07
申请人： Nicholas H. Tripsas , Matthew S. Buynoski , Suzette K. Pangrle , Uzodinma Okoroanyanwu , Angela T. Hui , Christopher F. Lyons , Ramkumar Subramanian , Sergey D. Lopatin , Minh Van Ngo , Ashok M. Khathuria , Mark S. Chang , Patrick K. Cheung , Jane V. Oglesby
发明人： Nicholas H. Tripsas , Matthew S. Buynoski , Suzette K. Pangrle , Uzodinma Okoroanyanwu , Angela T. Hui , Christopher F. Lyons , Ramkumar Subramanian , Sergey D. Lopatin , Minh Van Ngo , Ashok M. Khathuria , Mark S. Chang , Patrick K. Cheung , Jane V. Oglesby
IPC分类号： H01L2144
CPC分类号： H01L27/285 , H01L2924/0002 , H01L2924/00
摘要： One aspect of the present invention relates to a method of fabricating a polymer memory device in a via. The method involves providing a semiconductor substrate having at least one metal-containing layer thereon, forming at least one copper contact in the metal-containing layer, forming at least one dielectric layer over the copper contact, forming at least one via in the dielectric layer to expose at least a portion of the copper contact, forming a polymer material in a lower portion of the via, and forming a top electrode material layer in an upper portion of the via.
摘要翻译： 本发明的一个方面涉及在通孔中制造聚合物存储器件的方法。 该方法包括提供其上具有至少一个含金属层的半导体衬底，在含金属层中形成至少一个铜触点，在铜触点上形成至少一个电介质层，在电介质层中形成至少一个通孔 露出铜触点的至少一部分，在通孔的下部形成聚合物材料，并在通孔的上部形成顶部电极材料层。
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10.发明授权Materials and methods for sub-lithographic patterning of contact, via, and trench structures in integrated circuit devices 失效用于集成电路器件中接触，通孔和沟槽结构的亚光刻图案化的材料和方法公开(公告)号：US06767693B1
公开(公告)日：2004-07-27
申请号：US10208370
申请日：2002-07-30
IPC分类号： G03C556
CPC分类号： G03F7/26 , H01L21/0338 , H01L21/76802
摘要： An integrated circuit fabrication process including exposing a photoresist layer and providing a hydrophilic layer above the photoresist layer. The photoresist layer is exposed to a pattern of electromagnetic energy. The polymers in the hydrophilic layer can diffuse into the photoresist layer after provision of the hydrophilic layer. The diffusion can lead to plasticization of the photoresist layer polymers in exposed regions relative to unexposed regions. The process can be utilized to form a large variety of integrated circuit structures including via holes, trenches, contact holes and other features with wide process latitude and smooth feature side walls.
摘要翻译： 一种集成电路制造工艺，包括曝光光致抗蚀剂层并在光致抗蚀剂层之上提供亲水层。 光致抗蚀剂层暴露于电磁能的图案。 在提供亲水层之后，亲水层中的聚合物可以扩散到光致抗蚀剂层中。 扩散可导致相对于未曝光区域的曝光区域中的光致抗蚀剂层聚合物的增塑。 该方法可以用于形成各种各样的集成电路结构，包括通孔，沟槽，接触孔和具有宽工艺纬度和光滑特征侧壁的其它特征。
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