公开(公告)号：US20060249797A1

公开(公告)日：2006-11-09

申请号：US11389495

申请日：2006-03-27

申请人： Haruo Nakazawa ,  Kazuo Shimoyama ,  Manabu Takei

发明人： Haruo Nakazawa ,  Kazuo Shimoyama ,  Manabu Takei

IPC分类号： H01L29/732 ,  H01L21/8249

CPC分类号： H01L29/0661 ,  H01L29/045 ,  H01L29/0615 ,  H01L29/0657 ,  H01L29/66333 ,  H01L29/7395

摘要： On the top surface of a thin semiconductor wafer, top surface structures forming a semiconductor chip are formed. The top surface of the wafer is affixed to a supporting substrate with a double-sided adhesive tape. Then, from the bottom surface of the thin semiconductor wafer, a trench, which becomes a scribing line, is formed by wet anisotropic etching so that side walls of the trench are exposed. On the side walls of the trench with the crystal face exposed, an isolation layer with a conductivity type different from that of the semiconductor wafer for holding a reverse breakdown voltage is formed simultaneously with a collector region of the bottom surface diffused layer by ion implantation, followed by annealing with laser irradiation. The side walls form a substantially V-shaped or trapezoidal-shaped cross section, with an angle of the side wall relative to the supporting substrate being 30-70°. The double-sided adhesive tape is then removed from the top surface to produce semiconductor chips. With such a manufacturing method, a reverse-blocking semiconductor device having high reliability can be formed.

摘要翻译： 该方法包括在导电型半导体衬底的主表面中形成具有V形或梯形形状的横截面的沟槽。 将另一导电型半导体衬底引入到沟槽的侧壁中。 通过激光照射激活基板，其中沟槽的侧壁形成相对于主表面具有七十度或更小的倾斜角。 对于包括衬底的半导体器件也包括独立权利要求。

公开(公告)号：US08697558B2

公开(公告)日：2014-04-15

申请号：US12575730

申请日：2009-10-08

申请人： Haruo Nakazawa ,  Kazuo Shimoyama ,  Manabu Takei

发明人： Haruo Nakazawa ,  Kazuo Shimoyama ,  Manabu Takei

IPC分类号： H01L29/45

CPC分类号： H01L29/0661 ,  H01L29/045 ,  H01L29/0615 ,  H01L29/0657 ,  H01L29/66333 ,  H01L29/7395

摘要： On the top surface of a thin semiconductor wafer, top surface structures forming a semiconductor chip are formed. The top surface of the wafer is affixed to a supporting substrate with a double-sided adhesive tape. Then, from the bottom surface of the thin semiconductor wafer, a trench, which becomes a scribing line, is formed by wet anisotropic etching so that side walls of the trench are exposed. On the side walls of the trench with the crystal face exposed, an isolation layer with a conductivity type different from that of the semiconductor wafer for holding a reverse breakdown voltage is formed simultaneously with a collector region of the bottom surface diffused layer by ion implantation, followed by annealing with laser irradiation. The side walls form a substantially V-shaped or trapezoidal-shaped cross section, with an angle of the side wall relative to the supporting substrate being 30-70°. The double-sided adhesive tape is then removed from the top surface to produce semiconductor chips. With such a manufacturing method, a reverse-blocking semiconductor device having high reliability can be formed.

摘要翻译： 在薄的半导体晶片的顶表面上形成形成半导体芯片的顶表面结构。 晶片的上表面用双面胶带固定在支撑基板上。 然后，从薄的半导体晶片的底面开始，通过湿式各向异性蚀刻形成成为刻划线的沟槽，使得沟槽的侧壁露出。 在暴露了晶面的沟槽的侧壁上，通过离子注入与底面扩散层的集电极区域同时形成具有不同于用于保持反向击穿电压的半导体晶片的导电类型的隔离层， 然后用激光照射退火。 侧壁形成大致V形或梯形形状的横截面，侧壁相对于支撑基底的角度为30-70°。 然后从上表面去除双面胶带以制造半导体芯片。 通过这样的制造方法，可以形成具有高可靠性的反向阻挡半导体器件。

公开(公告)号：US08759870B2

公开(公告)日：2014-06-24

申请号：US12824541

申请日：2010-06-28

申请人： Haruo Nakazawa ,  Kazuo Shimoyama ,  Manabu Takei

发明人： Haruo Nakazawa ,  Kazuo Shimoyama ,  Manabu Takei

IPC分类号： H01L29/739 ,  H01L29/06

CPC分类号： H01L29/0661 ,  H01L29/045 ,  H01L29/0615 ,  H01L29/0657 ,  H01L29/66333 ,  H01L29/7395

摘要： On the top surface of a thin semiconductor wafer, top surface structures forming a semiconductor chip are formed. The top surface of the wafer is affixed to a supporting substrate with a double-sided adhesive tape. Then, from the bottom surface of the thin semiconductor wafer, a trench, which becomes a scribing line, is formed by wet anisotropic etching so that side walls of the trench are exposed. On the side walls of the trench with the crystal face exposed, an isolation layer with a conductivity type different from that of the semiconductor wafer for holding a reverse breakdown voltage is formed simultaneously with a collector region of the bottom surface diffused layer by ion implantation, followed by annealing with laser irradiation. The side walls form a substantially V-shaped or trapezoidal-shaped cross section, with an angle of the side wall relative to the supporting substrate being 30-70°. The double-sided adhesive tape is then removed from the top surface to produce semiconductor chips. With such a manufacturing method, a reverse-blocking semiconductor device having high reliability can be formed.

摘要翻译： 在薄的半导体晶片的顶表面上形成形成半导体芯片的顶表面结构。 晶片的上表面用双面胶带固定在支撑基板上。 然后，从薄的半导体晶片的底面开始，通过湿式各向异性蚀刻形成成为刻划线的沟槽，使得沟槽的侧壁露出。 在暴露了晶面的沟槽的侧壁上，通过离子注入与底面扩散层的集电极区域同时形成具有不同于用于保持反向击穿电压的半导体晶片的导电类型的隔离层， 然后用激光照射退火。 侧壁形成大致V形或梯形形状的横截面，侧壁相对于支撑基底的角度为30-70°。 然后从上表面去除双面胶带以制造半导体芯片。 通过这样的制造方法，可以形成具有高可靠性的反向阻挡半导体器件。

公开(公告)号：US08119496B2

公开(公告)日：2012-02-21

申请号：US12785932

申请日：2010-05-24

申请人： Kazuo Shimoyama ,  Manabu Takei ,  Haruo Nakazawa

发明人： Kazuo Shimoyama ,  Manabu Takei ,  Haruo Nakazawa

IPC分类号： H01L21/76

CPC分类号： H01L29/7393 ,  H01L21/30608 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0661 ,  H01L29/0834 ,  H01L29/402 ,  H01L29/66333 ,  H01L29/7395 ,  H01L2221/68327 ,  H01L2221/68381

摘要： A thin semiconductor wafer, on which a top surface structure and a bottom surface structure that form a semiconductor chip are formed, is affixed to a supporting substrate by a double-sided adhesive tape. Then, on the thin semiconductor wafer, a trench to become a scribing line is formed by wet anisotropic etching with a crystal face exposed so as to form a side wall of the trench. On the side wall of the trench with the crystal face thus exposed, an isolation layer for holding a reverse breakdown voltage is formed by ion implantation and low temperature annealing or laser annealing so as to be extended to the top surface side while being in contact with a p collector region as a bottom surface diffused layer. Then, laser dicing is carried out to neatly dice a collector electrode, formed on the p collector region, together with the p collector region, without presenting any excessive portions and any insufficient portions under the isolation layer. Thereafter, the double-sided adhesive tape is removed from the collector electrode to produce semiconductor chips. A highly reliable reverse-blocking semiconductor device can thus be formed at a low cost.

摘要翻译： 形成半导体芯片的上表面结构和底面结构的薄半导体晶片通过双面胶带固定在支撑基板上。 然后，在薄半导体晶片上，通过湿式各向异性蚀刻形成成为划刻线的沟槽，其中晶体面被暴露以形成沟槽的侧壁。 在具有如此露出的晶面的沟槽的侧壁上，通过离子注入和低温退火或激光退火形成用于保持反向击穿电压的隔离层，以便在与...接触的同时延伸到顶表面侧 ap集电极区域作为底面扩散层。 然后，进行激光切割，与集电体区域一起形成在集电极区域上的集电极整齐地切割，而不会在隔离层下方产生任何过量的部分和不足的部分。 此后，从集电极去除双面胶带以制造半导体芯片。 因此可以以低成本形成高度可靠的反向阻挡半导体器件。

公开(公告)号：US07776672B2

公开(公告)日：2010-08-17

申请号：US11389495

申请日：2006-03-27

申请人： Haruo Nakazawa ,  Kazuo Shimoyama ,  Manabu Takei

发明人： Haruo Nakazawa ,  Kazuo Shimoyama ,  Manabu Takei

IPC分类号： H01L21/336

CPC分类号： H01L29/0661 ,  H01L29/045 ,  H01L29/0615 ,  H01L29/0657 ,  H01L29/66333 ,  H01L29/7395

摘要： On the top surface of a thin semiconductor wafer, top surface structures forming a semiconductor chip are formed. The top surface of the wafer is affixed to a supporting substrate with a double-sided adhesive tape. Then, from the bottom surface of the thin semiconductor wafer, a trench, which becomes a scribing line, is formed by wet anisotropic etching so that side walls of the trench are exposed. On the side walls of the trench with the crystal face exposed, an isolation layer with a conductivity type different from that of the semiconductor wafer for holding a reverse breakdown voltage is formed simultaneously with a collector region of the bottom surface diffused layer by ion implantation, followed by annealing with laser irradiation. The side walls form a substantially V-shaped or trapezoidal-shaped cross section, with an angle of the side wall relative to the supporting substrate being 30-70°. The double-sided adhesive tape is then removed from the top surface to produce semiconductor chips. With such a manufacturing method, a reverse-blocking semiconductor device having high reliability can be formed.

摘要翻译： 在薄的半导体晶片的顶表面上形成形成半导体芯片的顶表面结构。 晶片的上表面用双面胶带固定在支撑基板上。 然后，从薄的半导体晶片的底面开始，通过湿式各向异性蚀刻形成成为刻划线的沟槽，使得沟槽的侧壁露出。 在暴露了晶面的沟槽的侧壁上，通过离子注入与底面扩散层的集电极区域同时形成具有不同于用于保持反向击穿电压的半导体晶片的导电类型的隔离层， 然后用激光照射退火。 侧壁形成大致V形或梯形形状的横截面，侧壁相对于支撑基底的角度为30-70°。 然后从上表面去除双面胶带以制造半导体芯片。 通过这样的制造方法，可以形成具有高可靠性的反向阻挡半导体器件。

公开(公告)号：US20060038206A1

公开(公告)日：2006-02-23

申请号：US11208459

申请日：2005-08-19

申请人： Kazuo Shimoyama ,  Manabu Takei ,  Haruo Nakazawa

发明人： Kazuo Shimoyama ,  Manabu Takei ,  Haruo Nakazawa

IPC分类号： H01L29/80

CPC分类号： H01L29/7393 ,  H01L21/30608 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0661 ,  H01L29/0834 ,  H01L29/402 ,  H01L29/66333 ,  H01L29/7395 ,  H01L2221/68327 ,  H01L2221/68381

摘要： A thin semiconductor wafer, on which a top surface structure and a bottom surface structure that form a semiconductor chip are formed, is affixed to a supporting substrate by a double-sided adhesive tape. Then, on the thin semiconductor wafer, a trench to become a scribing line is formed by wet anisotropic etching with a crystal face exposed so as to form a side wall of the trench. On the side wall of the trench with the crystal face thus exposed, an isolation layer for holding a reverse breakdown voltage is formed by ion implantation and low temperature annealing or laser annealing so as to be extended to the top surface side while being in contact with a p collector region as a bottom surface diffused layer. Then, laser dicing is carried out to neatly dice a collector electrode, formed on the p collector region, together with the p collector region, without presenting any excessive portions and any insufficient portions under the isolation layer. Thereafter, the double-sided adhesive tape is removed from the collector electrode to produce semiconductor chips. A highly reliable reverse-blocking semiconductor device can thus be formed at a low cost.

摘要翻译： 形成半导体芯片的上表面结构和底面结构的薄半导体晶片通过双面胶带固定在支撑基板上。 然后，在薄半导体晶片上，通过湿式各向异性蚀刻形成成为划刻线的沟槽，其中晶体面被暴露以形成沟槽的侧壁。 在具有如此露出的晶面的沟槽的侧壁上，通过离子注入和低温退火或激光退火形成用于保持反向击穿电压的隔离层，以便在与...接触的同时延伸到顶表面侧 ap集电极区域作为底面扩散层。 然后，进行激光切割，与集电体区域一起形成在集电极区域上的集电极整齐地切割，而不会在隔离层下方产生任何过量的部分和不足的部分。 此后，从集电极去除双面胶带以制造半导体芯片。 因此可以以低成本形成高度可靠的反向阻挡半导体器件。

公开(公告)号：US07741192B2

公开(公告)日：2010-06-22

申请号：US11208459

申请日：2005-08-19

申请人： Kazuo Shimoyama ,  Manabu Takei ,  Haruo Nakazawa

发明人： Kazuo Shimoyama ,  Manabu Takei ,  Haruo Nakazawa

IPC分类号： H01L21/76

CPC分类号： H01L29/7393 ,  H01L21/30608 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0661 ,  H01L29/0834 ,  H01L29/402 ,  H01L29/66333 ,  H01L29/7395 ,  H01L2221/68327 ,  H01L2221/68381

摘要： A thin semiconductor wafer, on which a top surface structure and a bottom surface structure that form a semiconductor chip are formed, is affixed to a supporting substrate by a double-sided adhesive tape. Then, on the thin semiconductor wafer, a trench to become a scribing line is formed by wet anisotropic etching with a crystal face exposed so as to form a side wall of the trench. On the side wall of the trench with the crystal face thus exposed, an isolation layer for holding a reverse breakdown voltage is formed by ion implantation and low temperature annealing or laser annealing so as to be extended to the top surface side while being in contact with a p collector region as a bottom surface diffused layer. Then, laser dicing is carried out to neatly dice a collector electrode, formed on the p collector region, together with the p collector region, without presenting any excessive portions and any insufficient portions under the isolation layer. Thereafter, the double-sided adhesive tape is removed from the collector electrode to produce semiconductor chips. A highly reliable reverse-blocking semiconductor device can thus be formed at a low cost.

摘要翻译： 形成半导体芯片的上表面结构和底面结构的薄半导体晶片通过双面胶带固定在支撑基板上。 然后，在薄半导体晶片上，通过湿式各向异性蚀刻形成成为划刻线的沟槽，其中晶体面被暴露以形成沟槽的侧壁。 在具有如此露出的晶面的沟槽的侧壁上，通过离子注入和低温退火或激光退火形成用于保持反向击穿电压的隔离层，以便在与...接触的同时延伸到顶表面侧 ap集电极区域作为底面扩散层。 然后，进行激光切割，与集电体区域一起形成在集电极区域上的集电极整齐地切割，而不会在隔离层下方产生任何过量的部分和不足的部分。 此后，从集电极去除双面胶带以制造半导体芯片。 因此可以以低成本形成高度可靠的反向阻挡半导体器件。

公开(公告)号：US20050059263A1

公开(公告)日：2005-03-17

申请号：US10876788

申请日：2004-06-24

申请人： Haruo Nakazawa ,  Mitsuaki Kirisawa ,  Kazuo Shimoyama

发明人： Haruo Nakazawa ,  Mitsuaki Kirisawa ,  Kazuo Shimoyama

IPC分类号： H01L21/268 ,  H01L21/331 ,  H01L21/31

CPC分类号： H01L29/66325 ,  H01L21/268

摘要： A method for stably activating pn-successive layers in a semiconductor element in a short time is disclosed. Pulsed beams, each of which has a pulse shape that is approximately rectangular, are projected from respective laser irradiation devices and successively combined into a pulsed beam equivalent to one pulse, with which the doped layer region is irradiated. By successively projecting the pulsed beams onto the doped layer region in this way, an effect is obtained which is the same as that of irradiating the doped layer region with a single pulsed beam having a long full-width at half maximum. A high activation ratio from a shallow region to a deep region of the doped layer region is enabled. This can stably activate the semiconductor element having the pn-successive layers as the doped layer region in a short time, making possible the manufacture of semiconductor elements having superior device characteristics.

摘要翻译： 公开了一种用于在短时间内稳定地激活半导体元件中的pn连续层的方法。 每个具有近似矩形的脉冲形状的脉冲光束从相应的激光照射装置投影，并且连续地组合成等效于掺杂层区域的一个脉冲的脉冲光束。 通过以这种方式将脉冲光束连续地投射到掺杂层区域上，获得的效果与用半个全长宽的单个脉冲光束照射掺杂层区域的效果相同。 能够实现从掺杂层区域的浅区域到深区域的高激活率。 这可以在短时间内稳定地激活具有pn连续层的半导体元件作为掺杂层区域，从而可以制造具有优异的器件特性的半导体元件。

公开(公告)号：US20070158740A1

公开(公告)日：2007-07-12

申请号：US11564053

申请日：2006-11-28

申请人： Koh Yoshikawa ,  Akio Sugi ,  Kouta Takahashi ,  Manabu Takei ,  Haruo Nakazawa ,  Noriyuki Iwamuro

发明人： Koh Yoshikawa ,  Akio Sugi ,  Kouta Takahashi ,  Manabu Takei ,  Haruo Nakazawa ,  Noriyuki Iwamuro

IPC分类号： H01L29/94 ,  H01L21/336

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7813

摘要： A semiconductor device including an n-type semiconductor substrate, a p-type channel region and a junction layer provided between the n-type semiconductor substrate and the p-type channel region is disclosed. The junction layer has n-type drift regions and p-type partition regions alternately arranged in the direction in parallel with the principal surface of the n-type semiconductor substrate. The p-type partition region forming the junction layer is made to have a higher impurity concentration than the n-type drift region. This enables the semiconductor device to have an enhanced breakdown voltage and, at the same time, have a reduced on-resistance.

摘要翻译： 公开了一种包括n型半导体衬底，p型沟道区和设置在n型半导体衬底和p型沟道区之间的结层的半导体器件。 接合层具有与n型半导体衬底的主表面平行的方向交替布置的n型漂移区和p型隔离区。 形成结层的p型分隔区的杂质浓度比n型漂移区高。 这使得半导体器件具有增强的击穿电压，并且同时具有降低的导通电阻。

公开(公告)号：US07535059B2

公开(公告)日：2009-05-19

申请号：US11564053

申请日：2006-11-28

申请人： Koh Yoshikawa ,  Akio Sugi ,  Kouta Takahashi ,  Manabu Takei ,  Haruo Nakazawa ,  Noriyuki Iwamuro

发明人： Koh Yoshikawa ,  Akio Sugi ,  Kouta Takahashi ,  Manabu Takei ,  Haruo Nakazawa ,  Noriyuki Iwamuro

IPC分类号： H01L29/76

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7813

摘要： A semiconductor device including an n-type semiconductor substrate, a p-type channel region and a junction layer provided between the n-type semiconductor substrate and the p-type channel region is disclosed. The junction layer has n-type drift regions and p-type partition regions alternately arranged in the direction in parallel with the principal surface of the n-type semiconductor substrate. The p-type partition region forming the junction layer is made to have a higher impurity concentration than the n-type drift region. This enables the semiconductor device to have an enhanced breakdown voltage and, at the same time, have a reduced on-resistance.

摘要翻译： 公开了一种包括n型半导体衬底，p型沟道区和设置在n型半导体衬底和p型沟道区之间的结层的半导体器件。 接合层具有与n型半导体衬底的主表面平行的方向交替布置的n型漂移区和p型隔离区。 形成结层的p型分隔区的杂质浓度比n型漂移区高。 这使得半导体器件具有增强的击穿电压，并且同时具有降低的导通电阻。