公开(公告)号：US4243474A

公开(公告)日：1981-01-06

申请号：US023883

申请日：1979-03-26

申请人： Haruo Shirai ,  Yoshikatsu Tanaka ,  Zinzo Kosuga ,  Kiyoshi Osaka

发明人： Haruo Shirai ,  Yoshikatsu Tanaka ,  Zinzo Kosuga ,  Kiyoshi Osaka

IPC分类号： H05K3/42 ,  H05K1/00 ,  H05K3/00 ,  H05K3/06 ,  H05K3/28 ,  H05K3/40 ,  B44C1/22 ,  C03C15/00 ,  C03C25/06 ,  C23F1/02

CPC分类号： H05K3/28 ,  H05K3/0064 ,  H05K3/0094 ,  H05K1/0393 ,  H05K2201/0305 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2203/068 ,  H05K3/4038 ,  H05K3/427 ,  H05K3/428 ,  Y10S428/902 ,  Y10T156/1056 ,  Y10T29/49156

摘要： This invention relates to a process of producing a printed wiring board having first and second electrically conductive circuit layers provided on an insulating laminate. The insulating laminate includes a first insulating layer having metal foils provided on both sides thereof and a second insulating layer which is attached to one of the sides of the first insulating layer so as to place one of the electrically conductive circuit layers between the first and second insulating layers. The first electrically conductive circuit layer is formed in a predetermined pattern by printing and etching one of the metal foils. Then, connecting through-holes are formed in the first insulating layer across the first electrically conductive circuit layer and the remaining metal foil. The second insulating layer is attached onto the first insulating layer so that the first electrically conductive circuit layer is covered with the second insulating layer. Thereafter the second electrically conductive circuit layer is formed in a predetermined pattern from the remaining metal foil by printing and etching.

摘要翻译： 本发明涉及一种制造印刷电路板的方法，该印刷电路板具有设置在绝缘层压板上的第一和第二导电电路层。 所述绝缘层叠体包括：第一绝缘层，其具有设置在其两侧的金属箔;以及第二绝缘层，其附接到所述第一绝缘层的一侧，以将所述导电电路层之一置于所述第一和第二绝缘层之间 绝缘层。 通过印刷和蚀刻金属箔之一，以预定图案形成第一导电电路层。 然后，跨越第一导电电路层和剩余的金属箔在第一绝缘层中形成连接通孔。 第二绝缘层被附着在第一绝缘层上，使得第一导电电路层被第二绝缘层覆盖。 此后，第二导电电路层通过印刷和蚀刻从剩余的金属箔以预定图案形成。