公开(公告)号：US20210118888A1

公开(公告)日：2021-04-22

申请号：US16658135

申请日：2019-10-20

申请人： HeFeChip Corporation Limited

发明人： John Zhang ,  Yanzun Li ,  GuoLiang Zhu ,  Tongqing Chen ,  Huang Liu

IPC分类号： H01L27/108

摘要： A semiconductor device including a silicon-on-insulator (SOI) wafer comprising a doped silicon substrate, a buried oxide layer on the doped silicon substrate, and a silicon device layer on the buried oxide layer. At least a trench capacitor is disposed in a trench of the SOI wafer. The trench capacitor penetrates through the buried oxide layer and extends into the doped silicon substrate. At least a select transistor is disposed on the silicon device layer. The select transistor includes a source doping region and a drain doping region, a channel region between the source doping region and the drain doping region, and a gate over the channel region. At least an embedded contact is disposed atop the trench capacitor to electrically couple the drain doping region of the select transistor with an inner electrode of the trench capacitor.

公开(公告)号：US12125873B2

公开(公告)日：2024-10-22

申请号：US17657641

申请日：2022-04-01

申请人： HeFeChip Corporation Limited

发明人： Liang Li ,  Chunhui Low ,  Huang Liu

IPC分类号： H01L21/84 ,  H01L21/8238 ,  H01L27/12 ,  H01L49/02 ,  H10B12/00

CPC分类号： H01L28/90 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1203 ,  H10B12/056 ,  H10B12/30 ,  H10B12/36 ,  H10B12/37

摘要： A method to form a fin structure on deep trenches (DTs) for a semiconductor device includes the following steps: A buried oxide layer (BOX) having the DTs, and silicon polies in the DTs is provided. A fin on the BOX and the silicon polies having poly fences is provided. A first mask is disposed on the fin. A liner is disposed on the BOX and the first mask, wherein the liner has a first part above the fin, a second part at lateral sides of the fin and a third part on the DTs and the BOX. A second mask is disposed on the first and the second parts of the liner. The second mask and the third parts of the liner are removed to reveal the first and the second parts of the liner. The poly fences are removed and spacers at the lateral sides are formed.

公开(公告)号：US11049862B2

公开(公告)日：2021-06-29

申请号：US16658135

申请日：2019-10-20

申请人： HeFeChip Corporation Limited

发明人： John Zhang ,  Yanzun Li ,  GuoLiang Zhu ,  Tongqing Chen ,  Huang Liu

IPC分类号： H01L27/108

摘要： A semiconductor device including a silicon-on-insulator (SOI) wafer comprising a doped silicon substrate, a buried oxide layer on the doped silicon substrate, and a silicon device layer on the buried oxide layer. An inner electrode and a node dielectric layer of a capacitor are disposed in a trench of the SOI wafer. The inner electrode and the node dielectric layer penetrate through the buried oxide layer and extend into the doped silicon substrate. At least a select transistor is disposed on the buried oxide layer. The select transistor includes a source doping region and a drain doping region, a channel region between the source doping region and the drain doping region, and a gate over the channel region. At least an embedded contact is disposed atop the capacitor to electrically couple the drain doping region of the select transistor with the inner electrode of the capacitor.

公开(公告)号：US20230240065A1

公开(公告)日：2023-07-27

申请号：US17586379

申请日：2022-01-27

申请人： HeFeChip Corporation Limited

发明人： Liang Li ,  John Zhang ,  Heng Yang ,  Huang Liu

IPC分类号： H01L27/108 ,  H01L21/3105

CPC分类号： H01L27/10829 ,  H01L27/10861 ,  H01L21/31053

摘要： A method of forming a plug for a semiconductor device and a semiconductor device thereof are disclosed. The proposed method of forming a plug for a semiconductor device, wherein the semiconductor device includes a deep trench (DT) structure and a storage node configured in the DT structure, comprising: (a) filling a single film in the DT structure and to cover the storage node; and (b) etching back the single film to form the plug located in the DT structure and around the storage node, wherein the single film forms a liner of a single type.

公开(公告)号：US11244947B1

公开(公告)日：2022-02-08

申请号：US17081004

申请日：2020-10-27

申请人： HeFeChip Corporation Limited

发明人： John Zhang ,  Devendra K Sadana ,  Yanzun Li ,  Huang Liu

IPC分类号： H01L27/108 ,  H01L29/66 ,  H01L29/16 ,  H01L29/06 ,  H01L29/04

摘要： A semiconductor device for a volatile memory is disclosed. The semiconductor device includes a substrate, a side wall and an epitaxial liner. The substrate has a first height and is made of a first material having a first lattice parameter. The side wall defines a deep trench. The epitaxial liner is disposed around the side wall, is made of a second material having a second lattice parameter, and has a second height having a same level with the first height, wherein the epitaxial liner and the side wall cooperate for creating a desired aspect ratio for the deep trench.