公开(公告)号：US20130168766A1

公开(公告)日：2013-07-04

申请号：US13543252

申请日：2012-07-06

申请人： Hee Bae LEE ,  Choul Joo Ko

发明人： Hee Bae LEE ,  Choul Joo Ko

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/1083 ,  H01L21/266 ,  H01L29/66659 ,  H01L29/7835

摘要： A drain extended MOS (DEMOS) transistor including at least one of: (1) A p-type epitaxial layer grown over an n-type semiconductor substrate. (2) An n-type well formed in a portion of the epitaxial layer. (3) A p-type drift region formed in another portion of the epitaxial layer. (4) A p-type source region formed in the well. (5) A p-type drain region formed in the drift region and spaced apart from the source region inside the epitaxial layer. (6) An n-type channel region extending between the drift region and the source region. (7) A gate structure formed over the channel region. (8) An n-type buried layer having a contact surface with the well and the drift region and formed in the epitaxial layer. A region of the buried layer has surface contact with the drift region and has a relatively low dopant concentration compared to other regions.

摘要翻译： 一种漏极扩展MOS（DEMOS）晶体管，包括以下中的至少一个：（1）在n型半导体衬底上生长的p型外延层。 （2）在外延层的一部分中形成的n型阱。 （3）形成在外延层的另一部分中的p型漂移区。 （4）在井中形成的p型源区。 （5）形成在漂移区中并与外延层内的源极区隔开的p型漏极区。 （6）在漂移区域和源极区域之间延伸的n型沟道区域。 （7）形成在通道区域上的栅极结构。 （8）具有与阱和漂移区的接触面并形成在外延层中的n型掩埋层。 掩埋层的区域与漂移区域具有表面接触，并且与其它区域相比具有相对较低的掺杂剂浓度。

公开(公告)号：US08569138B2

公开(公告)日：2013-10-29

申请号：US13543252

申请日：2012-07-06

申请人： Hee Bae Lee ,  Choul Joo Ko

发明人： Hee Bae Lee ,  Choul Joo Ko

IPC分类号： H01L21/336

CPC分类号： H01L29/1083 ,  H01L21/266 ,  H01L29/66659 ,  H01L29/7835

摘要： A drain extended MOS (DEMOS) transistor including at least one of: (1) A p-type epitaxial layer grown over an n-type semiconductor substrate. (2) An n-type well formed in a portion of the epitaxial layer. (3) A p-type drift region formed in another portion of the epitaxial layer. (4) A p-type source region formed in the well. (5) A p-type drain region formed in the drift region and spaced apart from the source region inside the epitaxial layer. (6) An n-type channel region extending between the drift region and the source region. (7) A gate structure formed over the channel region. (8) An n-type buried layer having a contact surface with the well and the drift region and formed in the epitaxial layer. A region of the buried layer has surface contact with the drift region and has a relatively low dopant concentration compared to other regions.

摘要翻译： 一种漏极扩展MOS（DEMOS）晶体管，包括以下中的至少一个：（1）在n型半导体衬底上生长的p型外延层。 （2）在外延层的一部分中形成的n型阱。 （3）形成在外延层的另一部分中的p型漂移区。 （4）在井中形成的p型源区。 （5）形成在漂移区中并与外延层内的源极区隔开的p型漏极区。 （6）在漂移区域和源极区域之间延伸的n型沟道区域。 （7）形成在通道区域上的栅极结构。 （8）具有与阱和漂移区的接触面并形成在外延层中的n型掩埋层。 掩埋层的区域与漂移区域具有表面接触，并且与其它区域相比具有相对较低的掺杂剂浓度。

公开(公告)号：US07601600B2

公开(公告)日：2009-10-13

申请号：US11590373

申请日：2006-10-30

申请人： Choul Joo Ko ,  Nam Joo Kim

发明人： Choul Joo Ko ,  Nam Joo Kim

IPC分类号： H01L29/76

CPC分类号： H01L27/0629 ,  H01L29/1083 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/7831 ,  H01L29/7835

摘要： Disclosed are a power semiconductor device and a method for manufacturing the same. The power semiconductor device has a PIP capacitor and an LDMOS transistor, the LDMOS transistor having second and third gate electrodes separate from a first gate electrode, which may be formed in the process of forming the upper electrode of the PIP capacitor, so it is possible to realize an LDMOS having a higher breakdown voltage and lower Ron and Rsp without additional processing. A drain voltage, which may be different from a voltage applied to the first gate electrode, may be applied to the third gate electrode, so it is possible to realize an LDMOS having a high breakdown voltage and low Ron and Rsp.

摘要翻译： 公开了功率半导体器件及其制造方法。 功率半导体器件具有PIP电容器和LDMOS晶体管，LDMOS晶体管具有与形成PIP电容器的上电极的过程中形成的第二和第三栅电极分离的第一和第三栅电极，因此可能 实现具有更高击穿电压的LDMOS和较低的Ron和Rsp，而无需额外的处理。 可以将不同于施加到第一栅电极的电压的漏极电压施加到第三栅电极，因此可以实现具有高击穿电压和低Ron和Rsp的LDMOS。

公开(公告)号：US07563667B2

公开(公告)日：2009-07-21

申请号：US12002241

申请日：2007-12-13

申请人： Choul Joo Ko ,  Yong Jun Lee

发明人： Choul Joo Ko ,  Yong Jun Lee

IPC分类号： H01L21/8234 ,  H01L21/8244 ,  H01L21/8242 ,  H01L21/336

CPC分类号： H01L27/0629 ,  H01L28/40

摘要： In a method for forming a semiconductor device, a device isolation layer is formed in a capacitor region of a silicon substrate, and a bottom electrode and a dielectric layer are formed on the device isolation layer. Insulation sidewalls are formed on both sides of the bottom electrode. A top electrode is formed on the dielectric layer, and simultaneously a gate electrode is formed in a transistor region of the silicon substrate. Source/drain impurity regions are formed in the silicon substrate at both sides of the gate electrode.

摘要翻译： 在形成半导体器件的方法中，在硅衬底的电容器区域中形成器件隔离层，并且在器件隔离层上形成底电极和电介质层。 绝缘侧壁形成在底部电极的两侧。 在电介质层上形成顶部电极，同时在硅衬底的晶体管区域形成栅电极。 源极/漏极杂质区域形成在栅极电极两侧的硅衬底中。

公开(公告)号：US20080176370A1

公开(公告)日：2008-07-24

申请号：US12002241

申请日：2007-12-13

申请人： Choul Joo Ko ,  Yong Jun Lee

发明人： Choul Joo Ko ,  Yong Jun Lee

IPC分类号： H01L21/76

CPC分类号： H01L27/0629 ,  H01L28/40

摘要： In a method for forming a semiconductor device, a device isolation layer is formed in a capacitor region of a silicon substrate, and a bottom electrode and a dielectric layer are formed on the device isolation layer. Insulation sidewalls are formed on both sides of the bottom electrode. A top electrode is formed on the dielectric layer, and simultaneously a gate electrode is formed in a transistor region of the silicon substrate. Source/drain impurity regions are formed in the silicon substrate at both sides of the gate electrode.

摘要翻译： 在形成半导体器件的方法中，在硅衬底的电容器区域中形成器件隔离层，在器件隔离层上形成底部电极和电介质层。 绝缘侧壁形成在底部电极的两侧。 在电介质层上形成顶部电极，同时在硅衬底的晶体管区域中形成栅电极。 源极/漏极杂质区域形成在栅极电极两侧的硅衬底中。

公开(公告)号：US08754474B2

公开(公告)日：2014-06-17

申请号：US13089005

申请日：2011-04-18

申请人： Choul Joo Ko

发明人： Choul Joo Ko

IPC分类号： H01L29/66

CPC分类号： H01L29/7816 ,  H01L21/76202 ,  H01L21/765 ,  H01L21/823456 ,  H01L21/823481 ,  H01L21/823493 ,  H01L29/0619 ,  H01L29/1083

摘要： A Lateral Double Diffused Metal-Oxide-Semiconductor (LDMOS) semiconductor device includes a substrate; a gate region, a source region, and a drain region on and/or over the substrate, a well region at one side of the drain region, and a guardring region disposed at one side of the well region and connected electrically to the well region.

摘要翻译： 横向双扩散金属氧化物半导体（LDMOS）半导体器件包括衬底; 在衬底上和/或上方的栅极区域，源极区域和漏极区域，漏极区域一侧的阱区域和设置在阱区域一侧的保护区域，并且电连接到阱区域 。

公开(公告)号：US07910466B2

公开(公告)日：2011-03-22

申请号：US11645657

申请日：2006-12-27

申请人： Choul Joo Ko

发明人： Choul Joo Ko

IPC分类号： H01L21/425

CPC分类号： H01L29/78 ,  H01L21/823412 ,  H01L21/823493

摘要： A high-voltage semiconductor device and a method for making the same are provided. A high-voltage semiconductor device and a low-voltage semiconductor device are formed in a single substrate, a photolithography process that is required to form a high-voltage well region is omitted, and the well region of the high-voltage semiconductor is formed together with the well region of the low-voltage semiconductor device formed in another photolithography process.

摘要翻译： 提供一种高压半导体器件及其制造方法。 在单个基板上形成高电压半导体器件和低电压半导体器件，省略了形成高电压阱区域所需的光刻工艺，并且高电压半导体的阱区域形成在一起 其中在另一光刻工艺中形成低电压半导体器件的阱区。

公开(公告)号：US20130082327A1

公开(公告)日：2013-04-04

申请号：US13252284

申请日：2011-10-04

申请人： Cheol Ho CHO ,  Choul Joo Ko

发明人： Cheol Ho CHO ,  Choul Joo Ko

IPC分类号： H01L29/78

CPC分类号： H01L29/0847 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor device including a first conductive epitaxial layer, a second conductive type first well provided in the first conductive epitaxial layer, a first conductive body provided in the first conductive epitaxial layer, a second conductive type drain extension region provided in the first conductive epitaxial layer and interposed between the first conductive body and the second conductive type first well, a second conductive type second well provided in the second conductive type first well, and a gate provided in the first conductive epitaxial layer.

摘要翻译： 一种半导体器件，包括第一导电外延层，设置在第一导电外延层中的第二导电类型第一阱，设置在第一导电外延层中的第一导电体，设置在第一导电外延层中的第二导电型漏极延伸区 并且介于所述第一导电体和所述第二导电型第一阱之间，设置在所述第二导电型第一阱中的第二导电型第二阱以及设置在所述第一导电外延层中的栅极。

公开(公告)号：US08227871B2

公开(公告)日：2012-07-24

申请号：US12631308

申请日：2009-12-04

申请人： Choul Joo Ko

发明人： Choul Joo Ko

IPC分类号： H01L27/092 ,  H01L29/76

CPC分类号： H01L29/7816 ,  H01L29/0619 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7817 ,  H01L29/7818

摘要： A semiconductor device and a method for manufacturing the same are disclosed. The semiconductor device includes a substrate having a first conductor-type, a buried layer of a second conductor-type on the substrate, a drain, and a first guard-ring on one side of the drain, a second guard-ring on one side of the first guard-ring, and a third guard-ring on one side of the second guard-ring.

摘要翻译： 公开了一种半导体器件及其制造方法。 半导体器件包括：衬底，其具有第一导体类型，衬底上第二导体类型的掩埋层，漏极和漏极一侧的第一保护环，一侧上的第二保护环 并且在第二保护环的一侧具有第三保护环。

公开(公告)号：US07687363B2

公开(公告)日：2010-03-30

申请号：US11639928

申请日：2006-12-15

申请人： Choul Joo Ko

发明人： Choul Joo Ko

IPC分类号： H01L21/336

CPC分类号： H01L29/6656 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7836

摘要： Disclosed is a method of manufacturing a semiconductor device, which includes the steps of: forming a high-voltage well region (e.g., by implanting impurity ions into a semiconductor substrate and then annealing); forming an isolation layer on the semiconductor substrate; implanting impurity ions into the high-voltage well region, thereby forming a low-voltage well region within the high-voltage well region; forming a gate electrode on the semiconductor substrate; and implanting impurity ions using the gate electrode as a mask, thereby forming source/drain regions within the low-voltage well region.

摘要翻译： 公开了一种制造半导体器件的方法，其包括以下步骤：形成高电压阱区（例如，通过将杂质离子注入到半导体衬底中然后退火）; 在所述半导体衬底上形成隔离层; 将杂质离子注入高电压阱区，从而在高电压阱区内形成低电压阱区; 在半导体衬底上形成栅电极; 以及使用栅极电极作为掩模注入杂质离子，从而在低电压阱区域内形成源极/漏极区域。