公开(公告)号：US08031553B2

公开(公告)日：2011-10-04

申请号：US12346986

申请日：2008-12-31

Applicant: Hee-Jin Byun

Inventor： Hee-Jin Byun

IPC: G11C8/00

CPC classification number: G11C7/22 ,  G11C7/1051 ,  G11C7/1054 ,  G11C7/1066 ,  G11C8/18

Abstract: A data strobe signal generating device includes a preamble controller configured to generate a preamble signal enabled in synchronization with a first clock signal and disabled in synchronization with a second clock signal after an output enable signal is enabled, and a data strobe signal output unit configured to generate a data strobe signal in response to the preamble signal.

Abstract translation: 数据选通信号产生装置包括：前置码控制器，被配置为产生与第一时钟信号同步使能的前导码信号，并且在输出使能信号被使能之后与第二时钟信号同步禁止;数据选通信号输出单元，被配置为 响应于前导信号产生数据选通信号。

公开(公告)号：US08547764B2

公开(公告)日：2013-10-01

申请号：US12647196

申请日：2009-12-24

Applicant: Jae-Woong Yun ,  Jong-Chern Lee ,  Hee-Jin Byun

Inventor： Jae-Woong Yun ,  Jong-Chern Lee ,  Hee-Jin Byun

IPC: G11C7/00

CPC classification number: G11C29/40 ,  G11C2029/2602

Abstract: A semiconductor memory device includes a plurality of data transmission lines, a plurality of parallel-to-serial conversion sections configured to receive, serially align, and output data from at least two of the plurality of data transmission lines, a plurality of data compression circuits configured to receive, compress, and output outputs of at least two of the plurality of parallel-to-serial conversion sections, and a plurality of data output circuits configured to output respective compression results of the plurality of data compression circuits to an outside of a chip.

Abstract translation: 半导体存储器件包括多个数据传输线，多个并行到串行转换部分，被配置为从所述多个数据传输线中的至少两个数据传输线接收串行对准和输出数据;多个数据压缩电路 被配置为接收，压缩和输出多个并行到串行转换部分中的至少两个的输出，以及多个数据输出电路，被配置为将多个数据压缩电路的各个压缩结果输出到 芯片。

公开(公告)号：US20110292740A1

公开(公告)日：2011-12-01

申请号：US12949143

申请日：2010-11-18

Applicant: Hee-Jin Byun ,  Jong-Chern Lee

Inventor： Hee-Jin Byun ,  Jong-Chern Lee

IPC: G11C7/10

CPC classification number: G11C7/1006 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093

Abstract: A semiconductor device includes a data alignment unit configured to align serial input data in response to a data strobe signal, a data latching unit configured to latch an output signal of the data alignment unit in response to first and second synchronization pulse signals which are activated according to BL information during a write operation, and a data output unit configured to output an output signal of the data latching unit to a plurality of global data lines in response to a data input strobe signal corresponding to the BL information.

Abstract translation: 半导体器件包括：数据对准单元，被配置为响应于数据选通信号对准串行输入数据;数据锁存单元，被配置为根据第一和第二同步脉冲信号来锁存数据对准单元的输出信号，所述第一和第二同步脉冲信号根据 到写入操作期间的BL信息，以及数据输出单元，被配置为响应于与BL信息对应的数据输入选通信号，将数据锁存单元的输出信号输出到多个全局数据线。

公开(公告)号：US08406080B2

公开(公告)日：2013-03-26

申请号：US12940727

申请日：2010-11-05

Applicant: Hee-Jin Byun

Inventor： Hee-Jin Byun

IPC: G11C7/22

CPC classification number: G11C7/22 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/222

Abstract: A semiconductor memory device using system clock with a high frequency can maintain a constant operation margin even in the change of operation environments including voltage level, temperature, and process. The semiconductor memory device includes an output control signal generator configured to be responsive to a read pulse that is activated in response to a read command, to generate an odd number of first output source signals corresponding to a rising edge of a system clock and a even number of second output source signals corresponding to a falling edge of the system clock, and an output enable signal generator configured to generate a first rising enable signal and a falling enable signal on the basis of the first output source signal and generate a second rising enable signal on the basis of the second output source signal, according to column address strobe (CAS) latencies, the first rising enable signal being activated earlier than the second rising enable signal by a half cycle of the system clock.

Abstract translation: 即使在包括电压水平，温度和过程的操作环境的变化中，使用具有高频率的系统时钟的半导体存储器件也可以保持恒定的操作余量。 半导体存储器件包括：输出控制信号发生器，被配置为响应于读取命令被激活的读取脉冲，以产生与系统时钟的上升沿对应的奇数个第一输出源信号， 与系统时钟的下降沿相对应的第二输出源信号的数量;以及输出使能信号发生器，被配置为基于第一输出源信号产生第一上升使能信号和下降使能信号，并产生第二上升使能 基于第二输出源信号的信号，根据列地址选通（CAS）延迟，第一上升使能信号比第二上升使能信号早于系统时钟的半个周期被激活。

公开(公告)号：US08164963B2

公开(公告)日：2012-04-24

申请号：US12647951

申请日：2009-12-28

Applicant: Hee-Jin Byun

Inventor： Hee-Jin Byun

IPC: G11C8/00

CPC classification number: G11C7/1051 ,  G11C7/1066 ,  G11C8/18

Abstract: A semiconductor memory device includes: a first strobe signal generation unit configured to generate a first rising strobe signal in response to a rising DLL clock signal; a second strobe signal generation unit configured to generate a second rising strobe signal in response to a falling DLL clock signal, the second rising strobe signal having an opposite phase to the first rising strobe signal and being activated at the same timing as the first rising strobe signal; a third strobe signal generation unit configured to generate a first falling strobe signal in response to the falling DLL clock signal; and a fourth strobe signal generation unit configured to generate a second falling strobe signal in response to the rising DLL clock signal, the second falling strobe signal having an opposite phase to the first falling strobe signal and being activated at the same timing as the first falling strobe signal.

Abstract translation: 半导体存储器件包括：第一选通信号生成单元，被配置为响应于升高的DLL时钟信号产生第一上升选通信号; 第二选通信号生成单元，被配置为响应于下降的DLL时钟信号产生第二上升选通信号，所述第二上升选通信号与所述第一上升选通信号具有相反相位，并且在与所述第一上升选通相同的定时被激活 信号; 第三选通信号生成单元，被配置为响应于所述下降的DLL时钟信号而产生第一下降选通信号; 以及第四选通信号生成单元，被配置为响应于所述升高的DLL时钟信号产生第二下降选通信号，所述第二下降选通信号具有与所述第一下降选通信号相反的相位，并且在与所述第一下降选通信号相同的定时被激活 频闪信号。

公开(公告)号：US07738315B2

公开(公告)日：2010-06-15

申请号：US11959269

申请日：2007-12-18

Applicant: Hee-Jin Byun

Inventor： Hee-Jin Byun

IPC: G11C8/00

CPC classification number: G11C7/1051 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222

Abstract: A circuit for generating an output enable signal in a semiconductor memory apparatus which can include an interval setting unit capable of delaying a burst length signal in synchronized with a clock, thereby generating an interval setting signal, and a signal generating unit for generating an output enable signal in response to a read command signal and the interval setting signal.

Abstract translation: 一种用于在半导体存储装置中产生输出使能信号的电路，该电路可以包括能够延迟与时钟同步的脉冲串长度信号的间隔设置单元，从而产生间隔设置信号，以及信号产生单元，用于产生输出使能 响应于读命令信号和间隔设置信号的信号。

公开(公告)号：US08509005B2

公开(公告)日：2013-08-13

申请号：US13249703

申请日：2011-09-30

Applicant: Hee-Jin Byun

Inventor： Hee-Jin Byun

IPC: G11C7/10

CPC classification number: G11C7/22 ,  G11C7/1051 ,  G11C7/1054 ,  G11C7/1066 ,  G11C8/18

Abstract: A data strobe signal generating device includes a preamble controller configured to generate a preamble signal enabled in synchronization with a first clock signal and disabled in synchronization with a second clock signal after an output enable signal is enabled, and a data strobe signal output unit configured to generate a data strobe signal in response to the preamble signal.

Abstract translation: 数据选通信号产生装置包括：前置码控制器，被配置为产生与第一时钟信号同步使能的前导码信号，并且在输出使能信号被使能之后与第二时钟信号同步禁止;数据选通信号输出单元，被配置为 响应于前导信号产生数据选通信号。

公开(公告)号：US20110103164A1

公开(公告)日：2011-05-05

申请号：US12647196

申请日：2009-12-24

Applicant: Jae-Woong YUN ,  Jong-Chern Lee ,  Hee-Jin Byun

Inventor： Jae-Woong YUN ,  Jong-Chern Lee ,  Hee-Jin Byun

IPC: G11C29/00 ,  G11C7/00

CPC classification number: G11C29/40 ,  G11C2029/2602

Abstract: A semiconductor memory device includes a plurality of data transmission lines, a plurality of parallel-to-serial conversion sections configured to receive, serially align, and output data from at least two of the plurality of data transmission lines, a plurality of data compression circuits configured to receive, compress, and output outputs of at least two of the plurality of parallel-to-serial conversion sections, and a plurality of data output circuits configured to output respective compression results of the plurality of data compression circuits to an outside of a chip.

Abstract translation: 半导体存储器件包括多个数据传输线，多个并行到串行转换部分，被配置为从所述多个数据传输线中的至少两个数据传输线接收串行对准和输出数据;多个数据压缩电路 被配置为接收，压缩和输出多个并行到串行转换部分中的至少两个的输出，以及多个数据输出电路，被配置为将多个数据压缩电路的各个压缩结果输出到 芯片。

公开(公告)号：US07852707B2

公开(公告)日：2010-12-14

申请号：US12128261

申请日：2008-05-28

Applicant: Hee-Jin Byun

Inventor： Hee-Jin Byun

IPC: G11C7/22

CPC classification number: G11C7/22 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/222

Abstract: A semiconductor memory device using system clock with a high frequency can maintain a constant margin of operation even with a changed operating environment including voltage level, temperature, and process. The semiconductor memory device includes a data output control circuit configured to control data outputted in synchronization with a falling edge of a system clock using a first output source signal corresponding to a rising edge of the system clock, and to control data outputted in synchronization with the rising edge of the system clock using a second output source signal corresponding to a falling edge of the system clock, and a data output circuit configured to output data, the data output circuit being controlled by the data output control circuit.

Abstract translation: 使用具有高频率的系统时钟的半导体存储器件即使在包括电压电平，温度和工艺的变化的工作环境下也能保持恒定的工作裕度。 半导体存储装置包括：数据输出控制电路，被配置为使用与系统时钟的上升沿相对应的第一输出源信号来控制与系统时钟的下降沿同步输出的数据，并且控制与 所述系统时钟的上升沿使用对应于所述系统时钟的下降沿的第二输出源信号，以及数据输出电路，被配置为输出数据，所述数据输出电路由所述数据输出控制电路控制。

公开(公告)号：US07843744B2

公开(公告)日：2010-11-30

申请号：US12165083

申请日：2008-06-30

Applicant: Hee-Jin Byun

Inventor： Hee-Jin Byun

IPC: G11C7/00

CPC classification number: G11C7/1072 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/1096 ,  G11C7/22

Abstract: A semiconductor memory device that generates a data strobe reset signal for preventing ring-back of a data strobe signal, and an operation method thereof. The semiconductor memory device includes a pulse signal generating unit for generating first and second pulse signals by synchronizing a write instruction with first and second internal clock signals, a reset signal generating unit for generating a reset signal having an activation width setup in response to the first and second pulse signals, and a data strobe reset signal generating unit for generating a data strobe reset signal by shifting the second pulse signal as much as a predetermined burst length and limiting an activation period of the data strobe reset signal in response to the reset signal.

Abstract translation: 一种产生用于防止数据选通信号反转的数据选通复位信号的半导体存储器件及其操作方法。 半导体存储器件包括脉冲信号产生单元，用于通过使写入指令与第一和第二内部时钟信号同步来产生第一和第二脉冲信号;复位信号产生单元，用于产生具有响应于第一和第二信号的激活宽度设置的复位信号 和第二脉冲信号，以及数据选通复位信号生成单元，用于通过将第二脉冲信号移位多达预定突发长度来产生数据选通复位信号，并且响应于复位信号限制数据选通复位信号的激活周期 。