SHIFT REGISTER CIRCUIT AND DRIVE METHOD THEREOF, SCAN DRIVE CIRCUIT AND DISPLAY DEVICE

    公开(公告)号:US20210027684A1

    公开(公告)日:2021-01-28

    申请号:US16077890

    申请日:2018-02-08

    IPC分类号: G09G3/20

    摘要: The present disclosure discloses a shift register circuit, a scan drive circuit, an array substrate and a display device. The shift register circuit has an input terminal and an output terminal, and includes: an input module connected to the input terminal and a first node when the input terminal is active, sets the first node to active; a reset module connected to the input terminal and a second node when the input terminal is active, sets the second node to inactive; an output module connected to the first node and the output terminal when the first node is active, sets the output terminal to active with a clock signal; a pull down module connected to the first node, the output terminal and the second node when the second node is active, sets the first node and the output terminal to inactive.

    ARRAY SUBSTRATE, METHOD FOR DRIVING THE SAME, AND DISPLAY APPARATUS

    公开(公告)号:US20190213968A1

    公开(公告)日:2019-07-11

    申请号:US16327773

    申请日:2018-04-28

    IPC分类号: G09G3/36

    摘要: The embodiments of the present disclosure disclose an array substrate, a method for driving the same, and a display apparatus. The array substrate includes: a plurality of data lines; a plurality of scanning lines intersecting the plurality of data lines to form a matrix array; a common electrode line; a plurality of pixel sub-circuits disposed at intersections of the data lines and the scanning lines, wherein each of the pixel sub-circuits comprises a pixel transistor and a pixel capacitor, wherein the pixel capacitor is connected between a corresponding one of the data lines and the common electrode line via the pixel transistor, and a control terminal of the pixel transistor is connected to a corresponding one of the scanning lines; and control sub-circuits, each connected between a respective data line and the common electrode line respectively and configured to zero a voltage difference across a pixel capacitor in each of pixel sub-circuits connected to the respective data line based on a control signal.