摘要:
An arrangement for adjusting a clock signal in a network element of a communications network includes a processor device arranged to produce a control variable containing information about synchronization messages received from at least two other network elements. A situation in which the reception from a sending network element of synchronization messages of a good enough quality ceases will not significantly disturb the clock signal to be adjusted because only part of the control variable used for the adjustment depends on synchronization messages sent by an individual network element. In a preferred arrangement, the reference value of the control variable is changed in response to a situation where the reception from a sending network element of synchronization messages of a good enough quality ceases. Thus it is possible to reduce the change of the difference between the control variable and its reference value which further reduces disturbances caused in the clock signal to be adjusted.
摘要:
A device for controlling a clock signal generator includes a processor (101) for forming at least two mutually different control quantities on the basis of reception moments of timing messages such as time stamps, where the reception moments are expressed as time values based on a first clock signal and the timing messages are transmitted in accordance with a second clock signal. The processor also calculates a weighted sum of the control quantities, and controls the clock signal generator with the weighted sum so as to synchronize the first clock signal and the second clock signal. The control quantities may represent, for example, a filtered value of observed phase-errors, a phase-error corresponding to a minimum observed transfer delay, and phase-errors corresponding to a given portion of the delay distribution. Using the weighted sum of the mutually different control quantities improves the utilization of the information content of the timing messages.
摘要:
The invention relates to a method and arrangement for transferring synchronizing information in a data transmission system including modem connections. The arrangement according to the invention comprises a modulator (207) that is arranged to generate an analog signal (222) modulated by synchronizing information, the frequency spectrum of said signal being located in a frequency range that falls outside the data transmission bands of the modem line connected to the network element. The arrangement includes a switching circuit (208) that is arranged to connect said analog signal to a data transmission cable (206) that forms part of said modem line connected to a network element. The arrangement includes a second switching circuit (209) that is arranged to receive said analog signal from a data transmission cable that forms part of the modem line connected to the second network element. The arrangement also includes a regenerator (209) that is arranged to regenerate said synchronizing information from said analog signal.
摘要:
The invention relates to determining a quantity to be measured from a communication system, such as a transmission delay or the phase difference of clock times. Measurement messages are transmitted (501, 502) between the two areas of the communication system in both transmission directions. Values of the time difference are calculated (503) for the measurement messages transmitted in at least one of the transmission directions, each of which values is the difference between the instant of reception measured at the reception and the instant of transmission measured at the transmission of the measurement message. The values of the time difference are used to calculate (504) an estimate of the distribution of the time difference, on the basis of which an estimate of the minimum value of the time difference is calculated (504).
摘要:
A device and a method for generating a secondary timing signal that is synchronous with a primary timing signal are presented. The method comprises deriving (401) an auxiliary timing signal from an auxiliary signal received at a first site and correcting (402, 403) the timing phase of the auxiliary timing signal so as to obtain the timing phase for the secondary timing signal. The timing phase is corrected with the aid of the following a) a constant phase shift between the auxiliary timing signal and another auxiliary timing signal derived in a second site where both the primary timing signal and the auxiliary signal are available and b) a dynamic phase shift between the other auxiliary timing signal and the primary timing signal at the second site.
摘要:
A device for controlling frequency synchronization includes a processor (101) for controlling a phase-controlled clock signal to achieve phase-locking between the phase-controlled clock signal and a reference clock signal, and for controlling a frequency-controlled clock signal so as to achieve frequency-locking between the frequency-controlled clock signal and the reference clock signal. The processor is also configured to monitor a deviation between the frequency- and phase-controlled clock signals, detect a change of circumstances such as temperature changes causing frequency drifting of the frequency-controlled clock signal, and replace or correct the frequency-controlled clock signal with or on the basis of the phase-controlled clock signal when both the monitored deviation and the detected change of circumstances show correlation confirming frequency drift of the frequency-controlled clock signal. Thus, the phase-controlled clock signal together with the information about possible changes in the circumstances is used for improving the quality of the frequency-controlled clock signal.
摘要:
A device for controlling frequency synchronization includes a processor for controlling a frequency-controlled clock signal on the basis of received timing messages so as to achieve frequency-locking between the frequency-controlled clock signal and a reference clock signal. For the purpose of finding such timing messages which have experienced similar transfer delays and thus are suitable for the frequency control, the processor is configured to control a phase-controlled clock signal on the basis of the timing messages so as to achieve phase-locking between the phase-controlled clock signal and the reference clock signal, and to select the timing messages to be used for the frequency control on the basis of phase-error indicators related to the phase control. Thus, the phase-controlled clock signal is an auxiliary clock signal that is utilized for performing the frequency control.
摘要:
The invention relates to transferring of a time of day value between network elements of a data transfer network. It has been surprisingly detected that the phase reference signals available to various network elements can be utilized in the synchronization of time of day values between these network elements. In the solution according to the invention, a first network element sends to a second network element a difference variable (401, 402, 403) that indicates how much the timing phase of the time of day value maintained in the first network element differs from the timing phase of the phase reference signal available to the first network element. In the second network element that receives the message, an estimate of the time of day value is formed (404, 405) based on the difference variable and the timing phase of the phase reference signal available to the second network element.
摘要:
A physical data transmission port in a network element of a data network, suited for realizing for instance both an electric packet switched Ethernet connection and an electric time slot switched E1/T1 connection. It has surprisingly been found out that the electric connector (101) and connected circuits provided in the network element can be arranged to support more than one wiring standard. For example the generally used RJ connector can be arranged to support both the RJ45 wiring standard and the RJ48c wiring standard, in which case, with the electric connector (101), there can be realized a physical data transmission port that is suited for realizing both an 10/100 Ethernet connection and an E1/T1 connection.