公开(公告)号：US06338102B1

公开(公告)日：2002-01-08

申请号：US09421075

申请日：1999-10-19

申请人： Henry Michael Garrett ,  William G. Holland ,  Joseph Franklin Logan ,  Joseph Gerald McDonald ,  John Kenneth Stacy

发明人： Henry Michael Garrett ,  William G. Holland ,  Joseph Franklin Logan ,  Joseph Gerald McDonald ,  John Kenneth Stacy

IPC分类号： G06F1310

CPC分类号： G06F5/065 ,  G06F3/06 ,  G06F2205/064 ,  G06F2205/066

摘要： A method for transferring data between non-contiguous buffers in a memory and an I/O device via a system I/O bus uses a descriptor queue stored in memory. Each descriptor points to a buffer and includes the length of the buffer. The I/O device is provided with the base address of the queue, the length of the queue and a current address which at initialization is the same as the base address. When data is to be transferred a device driver located in the processor sends the number of available descriptors (DescrEnq) to the I/O device which accesses the descriptors individually or in burst mode to gain access to the data buffers identified by the descriptors.

摘要翻译： 通过系统I / O总线在存储器和I / O设备中的非连续缓冲器之间传送数据的方法使用存储在存储器中的描述符队列。 每个描述符指向缓冲区并包括缓冲区的长度。 I / O设备提供队列的基地址，队列的长度以及初始化时的基址与基地址相同的当前地址。 当要传送数据时，位于处理器中的设备驱动程序将可用描述符（DescrEnq）的数量发送到单独或以突发模式访问描述符的I / O设备，以访问由描述符标识的数据缓冲区。

公开(公告)号：US5905913A

公开(公告)日：1999-05-18

申请号：US842348

申请日：1997-04-24

申请人： Henry Michael Garrett ,  William G. Holland ,  Joseph Franklin Logan ,  Joseph Gerald McDonald

发明人： Henry Michael Garrett ,  William G. Holland ,  Joseph Franklin Logan ,  Joseph Gerald McDonald

IPC分类号： G06F13/24 ,  G06F13/14

CPC分类号： G06F13/24

摘要： An interrupt mechanism associated with a peripheral devise is connected to a processor by an interrupt driven I/O bus. The mechanism includes an n input System Interrupt Status Register (SISR) which collects up to n different interrupts from the device during a predetermined time period. Gate and timing circuits under control of signals provided by the processor regulate the frequency of the interrupts thus reducing the number of interrupt operations required to service the device.

摘要翻译： 与外围设备相关联的中断机制通过中断驱动的I / O总线连接到处理器。 该机制包括一个n输入系统中断状态寄存器（SISR），它在预定的时间周期内从设备收集多达n个不同的中断。 由处理器提供的信号控制下的门和定时电路调节中断的频率，从而减少为设备提供服务所需的中断操作次数。

公开(公告)号：US06334162B1

公开(公告)日：2001-12-25

申请号：US09653733

申请日：2000-09-01

申请人： Henry Michael Garrett ,  William G. Holland ,  Joseph Franklin Logan ,  Joseph Gerald McDonald ,  John Kenneth Stacy

发明人： Henry Michael Garrett ,  William G. Holland ,  Joseph Franklin Logan ,  Joseph Gerald McDonald ,  John Kenneth Stacy

IPC分类号： G06F300

CPC分类号： G06F5/065 ,  G06F3/06 ,  G06F2205/064 ,  G06F2205/066

摘要： A method for transferring data between non-contiguous buffers in a memory and an I/O device via a system I/O bus uses a descriptor queue stored in memory. Each descriptor points to a buffer and includes the length of the buffer. The I/O device is provided with the base address of the queue, the length of the queue and a current address which at initialization is the same as the base address. When data is to be transferred a device driver located in the processor sends the number of available descriptors (DescrEnq) to the I/O device which accesses the descriptors individually or in burst mode to gain access to the data buffers identified by the descriptors.

摘要翻译： 通过系统I / O总线在存储器和I / O设备中的非连续缓冲器之间传送数据的方法使用存储在存储器中的描述符队列。 每个描述符指向缓冲区并包括缓冲区的长度。 I / O设备提供队列的基地址，队列的长度以及初始化时的基址与基地址相同的当前地址。 当要传送数据时，位于处理器中的设备驱动程序将可用描述符（DescrEnq）的数量发送到单独或以突发模式访问描述符的I / O设备，以访问由描述符标识的数据缓冲区。

公开(公告)号：US06272564B1

公开(公告)日：2001-08-07

申请号：US09420699

申请日：1999-10-19

申请人： Henry Michael Garrett ,  William G. Holland ,  Joseph Franklin Logan ,  Joseph Gerald McDonald ,  John Kenneth Stacy

发明人： Henry Michael Garrett ,  William G. Holland ,  Joseph Franklin Logan ,  Joseph Gerald McDonald ,  John Kenneth Stacy

IPC分类号： G06F1338

CPC分类号： G06F5/065 ,  G06F3/06 ,  G06F2205/064 ,  G06F2205/066

摘要： A method for transferring data between non-contiguous buffers in a memory and an I/O device via a system I/O bus uses a descriptor queue stored in memory. Each descriptor points to a buffer and includes the length of the buffer. The I/O device is provided with the base address of the queue, the length of the queue and a current address which at initialization is the same as the base address. When data is to be transferred a device driver located in the processor sends the number of available descriptors (DescrEnq) to the I/O device which accesses the descriptors individually or in burst mode to gain access to the data buffers identified by the descriptors.

摘要翻译： 通过系统I / O总线在存储器和I / O设备中的非连续缓冲器之间传送数据的方法使用存储在存储器中的描述符队列。 每个描述符指向缓冲区并包括缓冲区的长度。 I / O设备提供队列的基地址，队列的长度以及初始化时的基址与基地址相同的当前地址。 当要传送数据时，位于处理器中的设备驱动程序将可用描述符（DescrEnq）的数量发送到单独或以突发模式访问描述符的I / O设备，以访问由描述符标识的数据缓冲区。

公开(公告)号：US06163820A

公开(公告)日：2000-12-19

申请号：US419552

申请日：1999-10-19

申请人： Henry Michael Garrett ,  William G. Holland ,  Joseph Franklin Logan ,  Joseph Gerald McDonald ,  John Kenneth Stacy

发明人： Henry Michael Garrett ,  William G. Holland ,  Joseph Franklin Logan ,  Joseph Gerald McDonald ,  John Kenneth Stacy

IPC分类号： G06F3/06 ,  G06F5/06 ,  G06F13/14

CPC分类号： G06F5/065 ,  G06F3/06 ,  G06F2205/064 ,  G06F2205/066

摘要： A method for transferring data between non-contiguous buffers in a memory and an I/O device via a system I/O bus uses a descriptor queue stored in memory. Each descriptor points to a buffer and includes the length of the buffer. The I/O device is provided with the base address of the queue, the length of the queue and a current address which at initialization is the same as the base address. When data is to be transferred a device driver located in the processor sends the number of available descriptors (DescrEnq) to the I/O device which accesses the descriptors individually or in burst mode to gain access to the data buffers identified by the descriptors.

摘要翻译： 通过系统I / O总线在存储器和I / O设备中的非连续缓冲器之间传送数据的方法使用存储在存储器中的描述符队列。 每个描述符指向缓冲区并包括缓冲区的长度。 I / O设备提供队列的基地址，队列的长度以及初始化时的基址与基地址相同的当前地址。 当要传送数据时，位于处理器中的设备驱动程序将可用描述符（DescrEnq）的数量发送到单独或以突发模式访问描述符的I / O设备，以访问由描述符标识的数据缓冲区。

公开(公告)号：US6049842A

公开(公告)日：2000-04-11

申请号：US847034

申请日：1997-05-01

申请人： Henry Michael Garrett ,  William G. Holland ,  Joseph Franklin Logan ,  Joseph Gerald McDonald ,  John Kenneth Stacy

发明人： Henry Michael Garrett ,  William G. Holland ,  Joseph Franklin Logan ,  Joseph Gerald McDonald ,  John Kenneth Stacy

IPC分类号： G06F3/06 ,  G06F5/06 ,  G06F13/14

CPC分类号： G06F5/065 ,  G06F3/06 ,  G06F2205/064 ,  G06F2205/066

摘要： A method for transferring data between non-contiguous buffers in a memory and an I/O device via a system I/O bus uses a descriptor queue stored in memory. Each descriptor points to a buffer and includes the length of the buffer. The I/O device is provided with the base address of the queue, the length of the queue and a current address which at initialization is the same as the base address. When data is to be transferred a device driver located in the processor sends the number of available descriptors (DescrEnq) to the I/O device which accesses the descriptors individually or in burst mode to gain access to the data buffers identified by the descriptors.

公开(公告)号：US6073181A

公开(公告)日：2000-06-06

申请号：US868348

申请日：1997-06-03

申请人： William G. Holland ,  Joseph Franklin Logan ,  Joseph Gerald McDonald ,  Gregory Francis Paussa

发明人： William G. Holland ,  Joseph Franklin Logan ,  Joseph Gerald McDonald ,  Gregory Francis Paussa

IPC分类号： G06F11/14 ,  H04L12/56 ,  G06F15/16

CPC分类号： H04L49/9026 ,  H04L49/90 ,  H04L49/9021 ,  H04L49/9078 ,  H04L49/9084

摘要： A LAN adapter for transferring data frames from a LAN to memory buffers in a processor in which the LAN driver follows either the ODI or the NDIS specification. The adapter accumulates the frame length and compares this to the storage capacity of the buffer. If the frame length does not exceed the buffer capacity and the LAN driver implements the ODI specification, the adapter will indicate good status to the driver. If the frame length exceeds the buffer capacity the adapter will either send bad status to the ODI driver or reuse the buffer and send no status. If the driver follows NDIS, status is sent at the end of the frame.

摘要翻译： LAN适配器，用于将LAN中的数据帧传输到处理器中的内存缓冲区，其中LAN驱动程序遵循ODI或NDIS规范。 适配器累积帧长度，并将其与缓冲区的存储容量进行比较。 如果帧长度不超过缓冲区容量并且LAN驱动程序实现ODI规范，则适配器将向驱动程序指示良好的状态。 如果帧长度超过缓冲区容量，则适配器将向ODI驱动程序发送不良状态或重新使用缓冲区，并且不发送状态。 如果驱动程序遵循NDIS，则在帧结束时发送状态。

公开(公告)号：US08547825B2

公开(公告)日：2013-10-01

申请号：US13177680

申请日：2011-07-07

申请人： William J. Armstrong ,  John M. Borkenhagen ,  Martin J. Crippen ,  Dhruv M. Desai ,  David R. Engebretsen ,  Philip R. Hillier, III ,  William G. Holland ,  James E. Hughes ,  James A. O'Connor ,  Pravin S. Patel ,  Steven M. Tri

发明人： William J. Armstrong ,  John M. Borkenhagen ,  Martin J. Crippen ,  Dhruv M. Desai ,  David R. Engebretsen ,  Philip R. Hillier, III ,  William G. Holland ,  James E. Hughes ,  James A. O'Connor ,  Pravin S. Patel ,  Steven M. Tri

IPC分类号： G01R31/08

CPC分类号： H04L41/24 ,  H04L41/0659 ,  H04L49/15

摘要： Techniques are disclosed for managing a switch fabric. In one embodiment, a server system is provided that includes a midplane, one or more server cards, switch modules and a management controller. The midplane may include a fabric interconnect for a switch fabric. The one or more server cards and the switch modules may be operatively connected to the midplane. The switch modules may be configured to switch network traffic for the one or more server cards. The management controller may be configured to manage the switch modules via the fabric interconnect.

公开(公告)号：US07961612B2

公开(公告)日：2011-06-14

申请号：US11566338

申请日：2006-12-04

申请人： Mitchell L. Loeb ,  Harry Cheselka ,  William G. Holland ,  Norman C. Strole ,  Edward S. Suffern

发明人： Mitchell L. Loeb ,  Harry Cheselka ,  William G. Holland ,  Norman C. Strole ,  Edward S. Suffern

IPC分类号： G01R31/08

CPC分类号： H04L47/10 ,  H04L47/22 ,  H04L47/2441 ,  H04L47/30 ,  H04L47/31

摘要： An improved solution for limiting the transmission rate of data over a network is provided according to an aspect of the invention. In particular, the transmission rate for a port is limited by rate limiting one of a plurality of queues (e.g., class/quality of service queues) for the port, and directing all data (e.g., packets) for transmission through the port to the single rate limited queue. In this manner, the transmission rate for the port can be effectively limited to accommodate, for example, a lower transmission rate for a port on a destination node.

摘要翻译： 根据本发明的一个方面提供了一种用于限制网络上的数据传输速率的改进的解决方案。 特别地，端口的传输速率受限于端口的多个队列（例如，服务队列的类别/服务质量）之一的速率限制，并且引导所有数据（例如，分组）通过端口传输到 单速限制队列 以这种方式，可以有效地限制端口的传输速率，以适应例如目的地节点上的端口的较低传输速率。

公开(公告)号：US07484029B2

公开(公告)日：2009-01-27

申请号：US11351020

申请日：2006-02-09

申请人： William T. Boyd ,  Douglas M. Freimuth ,  William G. Holland ,  Steven W. Hunter ,  Renato J. Recio ,  Steven M. Thurber ,  Madeline Vega

发明人： William T. Boyd ,  Douglas M. Freimuth ,  William G. Holland ,  Steven W. Hunter ,  Renato J. Recio ,  Steven M. Thurber ,  Madeline Vega

IPC分类号： G06F13/36

CPC分类号： G06F9/5077

摘要： A computer-implemented method, apparatus, and computer usable program code are disclosed for migrating a virtual adapter from a source physical adapter to a destination physical adapter in a data processing system where multiple host computer systems share multiple adapters and communicate with those adapters through a PCI switched-fabric bus. The virtual adapter is first caused to stop processing transactions. All in-flight transactions that are associated with the virtual adapter are then captured. The configuration information that defines the virtual adapter is moved from the source physical adapter to the destination physical adapter. The in-flight transactions are then restored to their original locations on the destination virtual adapter. The virtual adapter is then restarted on the destination physical adapter such that the virtual adapter begins processing transactions.

摘要翻译： 公开了一种计算机实现的方法，装置和计算机可用程序代码，用于在数据处理系统中将虚拟适配器从源物理适配器迁移到目标物理适配器，其中多个主机计算机系统共享多个适配器并通过以下方式与这些适配器通信 PCI交换矩阵总线。 首先导致虚拟适配器停止处理事务。 然后捕获与虚拟适配器关联的所有飞行中事务。 定义虚拟适配器的配置信息从源物理适配器移动到目标物理适配器。 飞行中的事务然后恢复到目标虚拟适配器上的原始位置。 虚拟适配器然后在目标物理适配器上重新启动，以便虚拟适配器开始处理事务。