公开(公告)号：US07361604B2

公开(公告)日：2008-04-22

申请号：US10465852

申请日：2003-06-20

申请人： Henry Wei-Ming Chung ,  Shin-Yi Tsai ,  Ming-Chung Liang

发明人： Henry Wei-Ming Chung ,  Shin-Yi Tsai ,  Ming-Chung Liang

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： G03F7/405 ,  H01L21/0274 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0338

摘要： A semiconductor manufacturing method that includes depositing a first layer over a substrate, providing a layer of hardmask over the first layer, patterning and defining the hardmask layer to form at least two hardmask structures, wherein each hardmask structure includes at least one substantially vertical sidewall and one substantially horizontal top, and wherein the hardmask structures are separated by a first space, depositing a photo-insensitive material over the at least two hardmask structures and the first layer, wherein an amount of the photo-insensitive material deposited on the top of the hardmask structures is substantially greater than an amount of the photo-insensitive material deposited on the at least one sidewall of the hardmask structures, wherein the hardmask structures with the photo-insensitive layer on the sidewalls thereof are separated by a second space, and wherein the first space is greater than the second space.

摘要翻译： 一种半导体制造方法，包括在衬底上沉积第一层，在所述第一层上提供硬掩模层，图案化和限定所述硬掩模层以形成至少两个硬掩模结构，其中每个硬掩模结构包括至少一个基本垂直的侧壁和 一个基本上水平的顶部，并且其中所述硬掩模结构由第一空间分开，在所述至少两个硬掩模结构和所述第一层上沉积光敏材料，其中一定量的光敏材料沉积在 硬掩模结构基本上大于沉积在硬掩模结构的至少一个侧壁上的不敏感光材料的量，其中在其侧壁上具有光不敏感层的硬掩模结构被第二空间隔开，并且其中 第一空间大于第二空间。

公开(公告)号：US07033948B2

公开(公告)日：2006-04-25

申请号：US10739049

申请日：2003-12-19

申请人： Henry Wei-Ming Chung ,  Shin-Yi Tsai ,  Ming-Chung Liang

发明人： Henry Wei-Ming Chung ,  Shin-Yi Tsai ,  Ming-Chung Liang

IPC分类号： H01L21/302

CPC分类号： H01L21/0274 ,  G03F7/405 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0338 ,  Y10S438/947 ,  Y10S438/951

摘要： A semiconductor manufacturing method that includes defining a substrate, depositing a polysilicon layer over the substrate, depositing a layer of photoresist over the polysilicon layer, patterning and defining the photoresist layer, depositing a layer of inorganic material over the patterned and defined photoresist layer, wherein the layer of inorganic material is conformal and photo-insensitive, and anisotropic etching the layer of inorganic material and the layer of semiconductor material.

公开(公告)号：US07303995B2

公开(公告)日：2007-12-04

申请号：US10465850

申请日：2003-06-20

申请人： Henry Wei-Ming Chung ,  Shin-Yi Tsai ,  Ming-Chung Liang

发明人： Henry Wei-Ming Chung ,  Shin-Yi Tsai ,  Ming-Chung Liang

IPC分类号： H01L21/311 ,  H01L21/302

CPC分类号： G03F7/405 ,  H01L21/0274 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0338

摘要： A semiconductor manufacturing method that includes providing a substrate, providing a layer of material over the substrate, providing a layer of photoresist over the material layer, patterning and defining the photoresist layer, depositing a layer of polymer over the patterned and defined photoresist layer, wherein the layer of polymer is conformal and photo-insensitive, and etching the layer of polymer and the layer of material.

摘要翻译： 一种半导体制造方法，其包括提供衬底，在所述衬底上提供材料层，在所述材料层上提供光致抗蚀剂层，图案化和限定所述光致抗蚀剂层，在所述图案化和限定的光致抗蚀剂层上沉积聚合物层，其中 聚合物层是共形和不敏感的，并且蚀刻聚合物层和材料层。

公开(公告)号：US06750150B2

公开(公告)日：2004-06-15

申请号：US09978546

申请日：2001-10-18

申请人： Henry Wei-Ming Chung ,  Shin-Yi Tsai ,  Ming-Chung Liang

发明人： Henry Wei-Ming Chung ,  Shin-Yi Tsai ,  Ming-Chung Liang

IPC分类号： H01L211302

CPC分类号： H01L21/0274 ,  G03F7/405 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0338 ,  Y10S438/947 ,  Y10S438/951

摘要： A semiconductor manufacturing method that includes defining a substrate, depositing a polysilicon layer over the substrate, depositing a layer of photoresist over the polysilicon layer, patterning and defining the photoresist layer, depositing a layer of inorganic material over the patterned and defined photoresist layer, wherein the layer of inorganic material is conformal and photo-insensitive, and anisotropic etching the layer of inorganic material and the layer of semiconductor material.

公开(公告)号：US5666007A

公开(公告)日：1997-09-09

申请号：US487787

申请日：1995-06-07

申请人： Henry Wei-Ming Chung

发明人： Henry Wei-Ming Chung

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/52 ,  H01L23/535

CPC分类号： H01L21/76877 ,  H01L21/76805 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/53223 ,  H01L2924/0002 ,  Y10S257/915

摘要： A multilevel interconnect structure which has a first horizontal metallic conductor disposed on the top of a previously formed first contact/via dielectric where the contact/via dielectric contains a contact/via hole. A horizontal, interconnect is deposited over the first contact/via dielectric and has a first surface defined by the thickness and linewidth of the horizontal interconnect. A vertical metallic conductor is deposited in the contact/via hole to form a contact/via plug which extends through the dielectric and contacts the first surface of the horizontal interconnect. The process may be used to form additional levels and to form a plurality of similar horizontal and vertical metallic interconnects.

摘要翻译： 多层互连结构，其具有设置在先前形成的第一接触/通孔电介质的顶部上的第一水平金属导体，其中接触/通孔电介质包含接触/通孔。 水平的互连件沉积在第一接触/通孔电介质上，并且具有由水平互连件的厚度和线宽限定的第一表面。 垂直金属导体沉积在接触/通孔中以形成延伸穿过电介质并接触水平互连的第一表面的接触/通孔塞。 该过程可以用于形成附加水平并且形成多个类似的水平和垂直金属互连。

公开(公告)号：US06887627B2

公开(公告)日：2005-05-03

申请号：US10132156

申请日：2002-04-26

申请人： Henry Wei-Ming Chung ,  Chi-Yuan Hung ,  Ching-Yu Chang ,  I-Pien Wu

发明人： Henry Wei-Ming Chung ,  Chi-Yuan Hung ,  Ching-Yu Chang ,  I-Pien Wu

IPC分类号： G03F1/30 ,  G03F9/00

CPC分类号： G03F1/30

摘要： A method of fabricating a phase shift mask (PSM) is described. A patterned photoresist layer is formed on an opaque layer over a transparent plate. A thin mask layer is formed on the sidewalls of the patterned photoresist layer. The exposed opaque layer and transparent plate thereunder are then removed while using the patterned photoresist layer and mask layer as a mask. A phase shift opening is formed in the transparent plate, and thereby a phase shift layer is formed at the place where the phase shift opening is located. The patterned photoresist layer and the opaque layer thereunder are then removed to expose the transparent plate. The opaque layer under the mask layer can precisely self-align the phase shift layer to prevent alignment deviation caused by multiple lithography processes. The precision of the phase shift mask can be increased, and mask manufacture cost can be lowered.

摘要翻译： 描述了制造相移掩模（PSM）的方法。 在透明板上的不透明层上形成图案化的光致抗蚀剂层。 在图案化的光致抗蚀剂层的侧壁上形成薄的掩模层。 然后在使用图案化的光致抗蚀剂层和掩模层作为掩模的同时除去其下的暴露的不透明层和透明板。 在透明板中形成相移开口，由此在相移开口所在的位置形成相移层。 然后去除图案化的光致抗蚀剂层和其下的不透明层以暴露透明板。 掩模层下面的不透明层可以精确地自对准相移层，以防止由多个光刻工艺引起的对准偏差。 可以提高相移掩模的精度，并且可以降低掩模制造成本。

公开(公告)号：US5757077A

公开(公告)日：1998-05-26

申请号：US584914

申请日：1996-01-11

申请人： Henry Wei-Ming Chung ,  Kevin Carl Brown

发明人： Henry Wei-Ming Chung ,  Kevin Carl Brown

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/768 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/53223 ,  H01L2924/0002

摘要： A method of forming interconnecting layers in a semiconductor device whereby even if a via is misaligned with a metal line, a portion of the via not enclosed and capped by the metal is enclosed and capped by an etch stop spacer. The foundation layer includes a dielectric layer having a trench formed therein, the trench being filled with a plug material. The foundation layer further includes a barrier layer formed atop the dielectric layer. A metal layer is formed on the surface of the boundary layer, and a protection layer is formed on the surface of the metal layer. The protection layer and the metal layer are patterned to define a line of composite protection/metal on the surface of the boundary layer. An etch stop layer is formed which substantially conforms to the shape of the composite protection/metal line, including etch stop spacers conforming to the sidewall portions of the line. Selected portions of the etch stop layer are removed to expose the protection surface of the composite protection/metal line and portions of the boundary layer, while leaving the etch stop spacers. Portions of the boundary layer between the etch stop spacers are removed. A layer of via dielectric is formed that covers, and extends above, the line. A portion of the via dielectric layer above the composite protection/metal line is removed, exposing a portion of the protection surface of the composite protection/metal line. Finally, a portion of the protection surface from the composite protection/metal line is removed, leaving the metal portion of the line only.

公开(公告)号：US07605414B2

公开(公告)日：2009-10-20

申请号：US11042276

申请日：2005-01-24

申请人： Henry Wei-Ming Chung

发明人： Henry Wei-Ming Chung

IPC分类号： H01L29/76

CPC分类号： H01L21/76897 ,  H01L21/28061 ,  H01L21/823443 ,  H01L21/823475 ,  H01L29/78

摘要： A method for forming a self-aligned contact between two MOS transistors is described. The method supports the use of low-resistivity suicides for the formation of contacts in nanometer applications that employ polycide techniques. Silicon nitride and photoresist material act as dual masks in the formation of the self-aligned contact.

摘要翻译： 描述了在两个MOS晶体管之间形成自对准接触的方法。 该方法支持使用低电阻率硅胶在纳米应用中形成接触，这些应用采用多硅化物技术。 氮化硅和光致抗蚀剂材料在形成自对准接触时用作双重掩模。

公开(公告)号：US5691572A

公开(公告)日：1997-11-25

申请号：US590806

申请日：1996-01-24

申请人： Henry Wei-Ming Chung

发明人： Henry Wei-Ming Chung

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528

CPC分类号： H01L21/76877 ,  H01L21/76805 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/53223 ,  H01L2924/0002 ,  Y10S257/915

摘要： A multilevel interconnect structure which has a first horizontal metallic conductor disposed on the top of a previously formed first contact/via dielectric where the contact/via dielectric contains a contact/via hole. A horizontal interconnect is deposited over the first contact/via dielectric and has a first surface defined by the thickness and linewidth of the horizontal interconnect. A vertical metallic conductor is deposited in the contact/via hole to form a contact/via plug which extends through the dielectric and contacts the first surface of the horizontal interconnect. The process may be used to form additional levels and to form a plurality of similar horizontal and vertical metallic interconnects.

摘要翻译： 多层互连结构，其具有设置在先前形成的第一接触/通孔电介质的顶部上的第一水平金属导体，其中接触/通孔电介质包含接触/通孔。 横向互连沉积在第一接触/通孔电介质上，并且具有由水平互连的厚度和线宽限定的第一表面。 垂直金属导体沉积在接触/通孔中以形成延伸穿过电介质并接触水平互连的第一表面的接触/通孔塞。 该过程可以用于形成附加水平并且形成多个类似的水平和垂直金属互连。

公开(公告)号：US5646070A

公开(公告)日：1997-07-08

申请号：US400778

申请日：1995-03-06

申请人： Henry Wei-Ming Chung

发明人： Henry Wei-Ming Chung

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L29/78 ,  H01L29/43 ,  H01L21/822

CPC分类号： H01L23/53223 ,  H01L21/28518 ,  H01L23/485 ,  H01L2924/0002

摘要： A contact to a silicon semiconductor body is fabricated in a manner which merges the benefits of the low contact resistance provided by titanium silicide or cobalt silicide and the good step coverage provided by selective chemical vapor deposition (CVD) of tungsten or molybdenum from tungsten hexafluoride or molybdenum hexafluoride. An intermediate adhesion layer of molybdenum silicide or tungsten silicide is formed by physical vapor deposition, e.g., sputtering or vacuum evaporation, of molybdenum or titanium, followed by annealing. Such adhesion layer protects the underlying layer against damage by fluorine during CVD of the overlying layer of tungsten or molybdenum, as well as providing low resistance and good adhesion to both the underlying and overlying layers.

摘要翻译： 制造与硅半导体本体的接触，其结合了由硅化钛或硅化钴提供的低接触电阻的优点以及通过来自六氟化钨的钨或钼的选择性化学气相沉积（CVD）提供的良好的步骤覆盖，或 六氟化钼 通过钼或钛的物理气相沉积，例如溅射或真空蒸发，然后进行退火，形成硅化钼或硅化钨的中间粘合层。 这种粘合层在钨或钼的上覆层的CVD期间保护下层免受氟的损害，以及为底层和上覆层提供低电阻和良好的粘合性。