公开(公告)号：US6148426A

公开(公告)日：2000-11-14

申请号：US67671

申请日：1998-04-28

申请人： Heon-cheol Kim ,  Hong-shin Jun

发明人： Heon-cheol Kim ,  Hong-shin Jun

IPC分类号： G01R31/28 ,  G01R31/26 ,  G11C11/413 ,  G11C29/12 ,  G11C29/20

CPC分类号： G11C29/20

摘要： A memory address generator having a small chip area, a method for generating a memory address and a SRAM built-in self test (BIST) circuit using the same are described. When the number of addresses of a memory to be tested is 2.sup.n, where n is the number of bits in an address, the address generator includes an up counter for generating a first address of a series of sequentially increasing addresses, and an inverter for inverting the first address to generate a second address of a series of sequentially decreasing addresses. The address generator also includes a selector for selecting one of the first and second addresses, in response to a control signal, to output the selected address as an address of the memory. When the number of addresses of the memory to be tested is not 2.sup.n, the address generator includes an up counter for generating a first address of a series of sequentially increasing addresses up to a maximum address of the memory and a subtracter for subtracting the first address from the maximum address to generate a second address of a series of sequentially decreasing addresses. The address generator also includes a selector for selecting one of the first and second addresses, in response to control signal, to output the selected address as an address of the memory.

摘要翻译： 描述了具有小芯片面积的存储器地址发生器，用于产生存储器地址的方法和使用其的SRAM内置自测试（BIST）电路。 当要测试的存储器的地址数为2n时，其中n是地址中的位数，地址生成器包括用于产生一系列顺序增加地址的第一地址的上计数器，以及用于反转的反相器 所述第一地址生成一系列顺序减少的地址的第二地址。 地址生成器还包括用于响应于控制信号选择第一和第二地址之一的选择器，以将所选择的地址输出为存储器的地址。 当要测试的存储器的地址数不是2n时，地址生成器包括用于产生直到存储器的最大地址的一系列顺序增加的地址的第一地址的增加计数器和用于减去第一地址的减法器 从最大地址生成一系列顺序递减的地址的第二地址。 地址生成器还包括用于响应于控制信号选择第一和第二地址之一的选择器，以将所选择的地址输出为存储器的地址。

公开(公告)号：US06553530B1

公开(公告)日：2003-04-22

申请号：US09366252

申请日：1999-08-03

申请人： Heon-cheol Kim

发明人： Heon-cheol Kim

IPC分类号： G06F1100

CPC分类号： G01R31/31813 ,  G06F2201/83

摘要： Integrated circuit devices have a self-test capability in which a sequence of input data patterns are generated by a test pattern unit and are selectively applied to a functional or test block that is selected from a plurality of potential test blocks. The output data patterns that are generated by the selected test block are provided to a data compression unit that generates a signature in response thereto. This signature can then be compared with an expected pattern to determine whether the selected test block is functioning properly. Because the test pattern unit and the data compression unit are shared by a plurality of test blocks, the area normally reserved for test circuitry in an integrated circuit device can be reduced.

摘要翻译： 集成电路装置具有自检能力，其中输入数据模式序列由测试图案单元生成，并且被选择性地应用于从多个潜在测试块中选择的功能或测试块。 由所选择的测试块生成的输出数据模式被提供给响应于此生成签名的数据压缩单元。 然后可以将该签名与预期模式进行比较，以确定所选择的测试块是否正常工作。 由于测试图案单元和数据压缩单元由多个测试块共享，因此可以减少通常为集成电路设备中的测试电路预留的区域。

公开(公告)号：US5706293A

公开(公告)日：1998-01-06

申请号：US650936

申请日：1996-05-17

申请人： Heon-cheol Kim ,  Ho-ryong Kim ,  Sang-hyeon Baeg ,  Chang-hyun Cho

发明人： Heon-cheol Kim ,  Ho-ryong Kim ,  Sang-hyeon Baeg ,  Chang-hyun Cho

IPC分类号： G06F11/22 ,  G11C29/10 ,  G06F11/00

CPC分类号： G11C29/10

摘要： The present invention provides a test method of SOA (Single-Order Addressed) memory utilizing address data backgrounds applied to memory circuits. A memory test operation is performed using a total of (log.sub.2 N+1) address data backgrounds on an SOA memory having N mutually different addresses. Each address data background is written and read, then the inversion is written and read. Finally the address data background is again written and read for a total of 6 N(log.sub.2 N+1) operations.

摘要翻译： 本发明提供了利用应用于存储器电路的地址数据背景的SOA（单次寻址）存储器的测试方法。 在具有N个相互不同的地址的SOA存储器上使用总共（log2N + 1）地址数据背景来执行存储器测试操作。 写入和读取每个地址数据背景，然后写入和读取反转。 最后，地址数据背景再次写入和读取总共6 N（log2N + 1）操作。

公开(公告)号：US06338154B2

公开(公告)日：2002-01-08

申请号：US09060242

申请日：1998-04-14

申请人： Heon-cheol Kim

发明人： Heon-cheol Kim

IPC分类号： G01R3128

CPC分类号： G11C29/20

摘要： A memory address generating apparatus and method of a dynamic memory testing circuit for generating addresses for testing a dynamic memory which uses all the available addresses of the dynamic memory, which does not use the most significant addresses, and which does not use middle addresses among all the available addresses are provided. The address generator can obtain an up-counted address by up counting the addresses used by the dynamic memory. It can obtain a down-counted address by inverting the N-bit up-counted value, or by subtracting the N-bit up-counted value from the maximum address, or by combining the inverted MSB portion of the N-bit up-counted value with the LSB portion of the N-bit up-counted value subtracted from the LSB portion of the maximum address used in the dynamic memory. The down and up counted addresses are used as addresses for selectively testing the dynamic memory according to a selected testing method.

摘要翻译： 一种用于生成用于测试动态存储器的地址的动态存储器测试电路的存储器地址产生装置和方法，该动态存储器使用不使用最高有效地址的动态存储器的所有可用地址，并且不使用所有 提供可用的地址。 地址生成器可以通过对动态存储器使用的地址进行计数来获得递增计数的地址。 它可以通过反转N位向上计数值，或从最大地址减去N位向上计数值，或通过组合N位向上计数的反相MSB部分来获得递减计数的地址 从动态存储器中使用的最大地址的LSB部分中减去N位向上计数值的LSB部分的值。 根据所选择的测试方法，将向下和向上计数的地址用作有选择地测试动态存储器的地址。

公开(公告)号：US5754758A

公开(公告)日：1998-05-19

申请号：US638372

申请日：1996-04-26

申请人： Sang-Hyeon Baeg ,  Heon-cheol Kim ,  Ho-royng Kim ,  Chang-hyun Cho

发明人： Sang-Hyeon Baeg ,  Heon-cheol Kim ,  Ho-royng Kim ,  Chang-hyun Cho

IPC分类号： G06F12/16 ,  G06F13/00 ,  G11C29/32 ,  G01R31/28 ,  G06F11/22

CPC分类号： G11C29/32

摘要： A serial memory interface includes a register having a plurality of flip-flops forming a scan chain and coupled to both the input and output terminals of memory cells. An interlaced scan is established by interconnecting scan chains between multiple memory blocks. The interface structure provides a means for efficiently performing a built-in self test of an embedded memory while requiring minimal overhead in hardware structure.

摘要翻译： 串行存储器接口包括具有形成扫描链并耦合到存储器单元的输入和输出端的多个触发器的寄存器。 通过在多个存储器块之间互连扫描链来建立隔行扫描。 接口结构提供了一种有效地执行嵌入式存储器的内置自检的方式，同时在硬件结构中需要最小的开销。