公开(公告)号：US5706226A

公开(公告)日：1998-01-06

申请号：US777778

申请日：1996-12-31

Applicant: Tsiu Chiu Chan ,  Herman Ma

Inventor： Tsiu Chiu Chan ,  Herman Ma

IPC: G11C11/412 ,  H01L27/11 ,  G11C11/00

CPC classification number: G11C11/412 ,  H01L27/1104 ,  Y10S257/903

Abstract: A complementary-metal-oxide-semiconductor, static-random-access-memory cell has two pairs of n-channel and p-channel transistors in complementary symmetry, push-pull arrangement. One pair of complementary transistors stores the binary state of the memory cell, and the other pair of complementary transistors stores the complement of the binary state of the memory cell. Both transistors in each of the complementary pairs of complementary transistors in the memory cell have nearly equal current carrying capacity and provide a voltage trip point for a change of state of the memory cell equal to approximately 1/2 the bias voltage across the memory cell. Complementary word lines and bit lines select a memory cell for reading or writing. The wordline control gates have complementary transistors, and those complementary transistors push or pull current to the memory cell in parallel to minimize the effect of transistor threshold voltage on the flow of current to the complementary transistors in the memory cell. A pair of transmission gates are connected one each to each of the complementary bit lines. Each transmission gate has a pair of complementary transistors and an actuation input. The transmission gates upon actuation passing voltages on complementary bit-lines indicative of the state of the memory cell.

Abstract translation: 互补金属氧化物半导体，静态随机存取存储器单元具有互补对称的推挽布置的两对n沟道和p沟道晶体管。 一对互补晶体管存储存储单元的二进制状态，另一对互补晶体管存储存储单元的二进制状态的补码。 存储单元中互补晶体管互补对中的每个互补晶体管中的两个晶体管具有几乎相等的载流容量，并且为存储器单元的状态改变等于所述存储单元两端的偏置电压的大约1/2提供电压跳变点。 互补字线和位线选择用于读取或写入的存储单元。 字线控制栅极具有互补晶体管，并且那些互补晶体管并联推或拉电流到存储器单元以最小化晶体管阈值电压对存储器单元中互补晶体管的电流的影响。 一对传输门一个连接到每个互补位线。 每个传输门具有一对互补晶体管和致动输入。 驱动时的传输门通过指示存储器单元的状态的互补位线上的电压。

公开(公告)号：US20050088872A1

公开(公告)日：2005-04-28

申请号：US10695238

申请日：2003-10-27

Applicant: Herman Ma

Inventor： Herman Ma

IPC: G11C13/00 ,  G11C16/02 ,  G11C16/26 ,  H01L27/105 ,  G11C5/00

CPC classification number: G11C13/0004 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/79

Abstract: A circuit and method are disclosed for a memory device, such as a phase change memory. Specifically, there is disclosed a memory having a plurality of columns of memory cells, with each column of memory cells being coupled to a bit or data line. Each memory cell includes a programmable resistive element coupled in series with a select transistor. Each bit line is coupled to a distinct reference cell and a distinct transistor. The transistor is coupled between the corresponding bit line and a reference voltage, such as ground. During a memory read operation, the transistor, reference cell and addressed memory cell form a differential amplifier circuit. The output of the differential amplifier circuit is coupled to the data output terminals of the phase change memory.

Abstract translation: 公开了一种用于诸如相变存储器之类的存储器件的电路和方法。 具体地，公开了具有多列存储器单元的存储器，每列存储器单元耦合到位或数据线。 每个存储单元包括与选择晶体管串联耦合的可编程电阻元件。 每个位线耦合到不同的参考单元和不同的晶体管。 晶体管耦合在对应的位线和参考电压之间，例如接地。 在存储器读取操作期间，晶体管，参考单元和寻址的存储单元形成差分放大器电路。 差分放大器电路的输出耦合到相变存储器的数据输出端子。

公开(公告)号：US4896060A

公开(公告)日：1990-01-23

申请号：US264902

申请日：1988-10-31

Applicant: Herman Ma

Inventor： Herman Ma

IPC: H03K19/177 ,  H04M1/26 ,  H04M1/27

CPC classification number: H04M1/26

Abstract: An option select circuit for a dialer includes an internal address generator (20) for generating an address pattern, which, in a set up mode, is output from a multiplexer (14) to I/O pins (10). The pins (10) are selectively hardwired through an interface circuit (24) back to address input pins (50) and (52) for input to a decorder (28). The decoder (28) decodes the selected address for input to a PLA (30). This allows selection of various functions in a function generator (12) for operation in the normal dialer mode. The interface circuit (24) comprises hardwire connections (54) and (56).

公开(公告)号：US06985389B2

公开(公告)日：2006-01-10

申请号：US10695238

申请日：2003-10-27

Applicant: Herman Ma

Inventor： Herman Ma

IPC: G11C7/00

CPC classification number: G11C13/0004 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/79

Abstract: A circuit and method are disclosed for a memory device, such as a phase change memory. Specifically, there is disclosed a memory having a plurality of columns of memory cells, with each column of memory cells being coupled to a bit or data line. Each memory cell includes a programmable resistive element coupled in series with a select transistor. Each bit line is coupled to a distinct reference cell and a distinct transistor. The transistor is coupled between the corresponding bit line and a reference voltage, such as ground. During a memory read operation, the transistor, reference cell and addressed memory cell form a differential amplifier circuit. The output of the differential amplifier circuit is coupled to the data output terminals of the phase change memory.

Abstract translation: 公开了一种用于诸如相变存储器之类的存储器件的电路和方法。 具体地，公开了具有多列存储器单元的存储器，每列存储器单元耦合到位或数据线。 每个存储单元包括与选择晶体管串联耦合的可编程电阻元件。 每个位线耦合到不同的参考单元和不同的晶体管。 晶体管耦合在对应的位线和参考电压之间，例如接地。 在存储器读取操作期间，晶体管，参考单元和寻址的存储单元形成差分放大器电路。 差分放大器电路的输出耦合到相变存储器的数据输出端子。

公开(公告)号：USRE36443E

公开(公告)日：1999-12-14

申请号：US903528

申请日：1997-07-30

Applicant: Herman Ma ,  Darin L. Kincaid ,  David N. Larson

Inventor： Herman Ma ,  Darin L. Kincaid ,  David N. Larson

IPC: H04M1/2745 ,  H03K19/01 ,  H03K3/26

CPC classification number: H04M1/2745

Abstract: An option select circuit for a dialer includes an internal address generator (20) for generating an address pattern, which, in a set up mode, is output from a multiplexer (14) to I/O pins (10). The pins (10) are selectively hardwired through an interface circuit (24) back to address input pins (50) and (52) for input to a decorder (28). The decoder (28) decodes the selected address for input to a PLA (30). This allows selection of various functions in a function generator (12) for operation in the normal dialer mode. The interface circuit (24) comprises hardwire connections (54) and (56).

Abstract translation: 用于拨号器的选项选择电路包括用于产生地址模式的内部地址发生器（20），其在建立模式中从多路复用器（14）输出到I / O引脚（10）。 引脚（10）通过接口电路（24）选择性地硬连接回到输入引脚（50）和（52）以输入到解码器（28）。 解码器（28）对所选择的地址进行解码以输入到PLA（30）。 这允许在功能发生器（12）中选择用于在正常拨号器模式下操作的各种功能。 接口电路（24）包括硬线连接（54）和（56）。