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6 条记录 (耗时 0.014 秒)

    Measuring instrument for fill level sensors
    3.
    发明授权
    Measuring instrument for fill level sensors 有权
    液位传感器测量仪

    公开(公告)号：US06404209B1

    公开(公告)日：2002-06-11

    申请号：US09597068

    申请日：2000-06-20

    申请人： Juergen Klattenhoff ,  Guenter Schmitz ,  Holger Schroeter

    发明人： Juergen Klattenhoff ,  Guenter Schmitz ,  Holger Schroeter

    IPC分类号： G01R2700

    CPC分类号： G01F23/243 ,  G01R17/02

    摘要： A measuring instrument (11) for fill level sensors (4) having a measuring electrode (6) and a compensating electrode (9). The measuring instrument (11) has a bridge circuit whose one bridge branch (21) is formed by two series-connected test resistors (23, 24). The other bridge branch (22) is formed by the measuring resistor (17) on the measuring electrode (6) and the compensating resistor (18) on the compensating electrode (9). Between the two bridge branches (21, 22) a diagonal line (26) with a test switch (27) is provided. The measuring instrument (11) is controlled by the control circuit (13) so that the diagonal line (26) is closed outside of preset test time periods, and interrupted at preset test time periods. The end of the diagonal line (26) located between the two test resistors (23, 24) is connected to the base potential (25) of the measuring circuit (12). The resistors (17, 18, 23, 24) are designed so that when the test switch (27) is closed, the imbalance of the bridge is determined by the second bridge branch (22), whereas when the test switch (27) is open, the imbalance of the bridge is determined by the first bridge branch (21), simulating in this way a situation in which the fill level has dropped below the limit value. The control circuit (13) provides an error signal if the signal of measuring circuit (12) is not corresponding. In this way, the measuring instrument (11) automatically tests its functionality.

    摘要翻译： 一种用于具有测量电极（6）和补偿电极（9）的填充液位传感器（4）的测量仪器（11）。 测量仪器（11）具有桥式电路，其桥式分支（21）由两个串联连接的测试电阻（23,24）形成。 另一桥分支（22）由测量电极（6）上的测量电阻（17）和补偿电极（9）上的补偿电阻（18）形成。 在两个桥接支路（21,22）之间，提供了带有测试开关（27）的对角线（26）。 测量仪器（11）由控制电路（13）控制，使得对角线（26）在预设测试时间段之外关闭，并在预设的测试时间段中断。 位于两个测试电阻器（23,24）之间的对角线（26）的端部连接到测量电路（12）的基极（25）。 电阻器（17,18,23,24）被设计成使得当测试开关（27）闭合时，桥接器的不平衡由第二桥接支路（22）确定，而当测试开关（27）为 开放，桥梁的不平衡由第一桥梁分支（21）确定，模拟这种填充水平已经降到极限值以下的情况。 如果测量电路（12）的信号不对应，则控制电路（13）提供误差信号。 以这种方式，测量仪器（11）自动测试其功能。

    Oscillator circuit with laser-trimmable load impedance
    4.
    发明授权
    Oscillator circuit with laser-trimmable load impedance 失效
    具有激光可调负载阻抗的振荡器电路

    公开(公告)号：US07170354B2

    公开(公告)日：2007-01-30

    申请号：US10741495

    申请日：2003-12-19

    申请人： Holger Schroeter ,  Ingo Skuras

    发明人： Holger Schroeter ,  Ingo Skuras

    IPC分类号： H03L7/00

    CPC分类号： H01G4/33 ,  H03B5/1841 ,  H03B2201/0208

    摘要： An oscillator circuit for generating signals with a predetermined oscillator frequency is provided. The oscillator circuit has at least one resonator and at least one load impedance connected to the resonator. The oscillator circuit may be fully automatically trimmed and economically produced and, moreover, is of an improved quality wherein the load impedance comprises at least one structure which may be machined by means of high-energy radiation to trim the resonant characteristics of the oscillator circuit.

    摘要翻译： 提供了用于产生具有预定振荡器频率的信号的振荡器电路。 振荡器电路具有至少一个谐振器和至少一个连接到谐振器的负载阻抗。 振荡器电路可以被完全自动修整和经济地制造，此外，具有改进的质量，其中负载阻抗包括至少一个结构，其可以通过高能辐射加工以修整振荡器电路的谐振特性。

    Stacked semiconductor memory device
    5.
    发明申请
    Stacked semiconductor memory device 审中-公开
    堆叠半导体存储器件

    公开(公告)号：US20060255459A1

    公开(公告)日：2006-11-16

    申请号：US11126408

    申请日：2005-05-11

    申请人： Simon Muff ,  Srdjan Djordjevic ,  Holger Schroeter ,  Siva RaghuRam

    发明人： Simon Muff ,  Srdjan Djordjevic ,  Holger Schroeter ,  Siva RaghuRam

    IPC分类号： H01L23/48

    CPC分类号： G11C5/02 ,  H01L25/105 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/0102 ,  H01L2924/01021 ,  H01L2924/01068 ,  H01L2924/3025 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

    摘要： A stacked semiconductor memory device includes memory device contacts to externally connect the stacked semiconductor memory device to a printed circuit board. In a dual or quad stack configuration, the stacked semiconductor memory device includes a first package which is stacked above a second package. The first and second packages are preferably designed as FBGA packages, each of them including package contacts. By providing first and second flexible circuit structures to connect the package contacts of the first and second packages to the memory device contacts, a symmetrical stacked package configuration is obtained. This configuration facilitates transmission of signals with improved signal integrity via a bus of the printed circuit board between the stacked semiconductor memory device and a controller chip, even if the frequency of the bus or the load of the stacked semiconductor memory is increased.

    摘要翻译： 堆叠的半导体存储器件包括用于将堆叠的半导体存储器件外部连接到印刷电路板的存储器件触点。 在双堆叠或四堆叠配置中，堆叠的半导体存储器件包括堆叠在第二封装之上的第一封装。 第一和第二封装优选地被设计为FBGA封装，其中每个包括封装触点。 通过提供第一和第二柔性电路结构来将第一和第二封装的封装触点连接到存储器件触点，获得了对称的堆叠封装结构。 即使总线的频率或层叠的半导体存储器的负载增加，这种配置便于通过印刷电路板的总线在堆叠的半导体存储器件和控制器芯片之间传输具有改善的信号完整性的信号。