公开(公告)号：US09086843B2

公开(公告)日：2015-07-21

申请号：US14111071

申请日：2012-04-10

申请人： Balaji Kanigicherla ,  Siva Raghuram Voleti ,  Manohar Kotta ,  Murthy Dhulipala ,  Suman Kopparapu

发明人： Balaji Kanigicherla ,  Siva Raghuram Voleti ,  Manohar Kotta ,  Murthy Dhulipala ,  Suman Kopparapu

IPC分类号： G06F3/16

CPC分类号： G06F3/162 ,  G06F3/165

摘要： Described herein is a multi-host computing system (100) having multiple host processors running different operating systems. In one implementation, a method of playing audio streams received from a plurality of hosts of a multi-host computing system (100), the method comprising receiving a second audio stream from a second host, and changing audio stream parameters associated with the second audio stream from second host to match the corresponding parameter values associated with a first audio stream received from a first host to generate an updated second audio stream. The method further comprises mixing the updated second audio stream with the first audio stream to generate a combined audio stream, and playing the combined audio stream using at least one audio codec (104) of the multi-host computing system (100).

摘要翻译： 这里描述的是具有运行不同操作系统的多个主机处理器的多主机计算系统（100）。 在一个实现中，一种播放从多主机计算系统（100）的多个主机接收的音频流的方法，所述方法包括从第二主机接收第二音频流，以及改变与所述第二音频相关联的音频流参数 流从第二主机匹配与从第一主机接收的第一音频流相关联的对应参数值，以生成更新的第二音频流。 该方法还包括将更新的第二音频流与第一音频流混合以产生组合音频流，以及使用多主机计算系统（100）中的至少一个音频编解码器（104）播放组合音频流。

公开(公告)号：US08972624B2

公开(公告)日：2015-03-03

申请号：US14111404

申请日：2012-04-09

申请人： Balaji Kanigicherla ,  Siva Raghuram Voleti ,  Surya Narayana Dommeti ,  Krishna Mohan Tandaboina ,  Rajani Lotti

发明人： Balaji Kanigicherla ,  Siva Raghuram Voleti ,  Surya Narayana Dommeti ,  Krishna Mohan Tandaboina ,  Rajani Lotti

IPC分类号： G06F3/00 ,  G06F13/28 ,  G06F13/10

CPC分类号： G06F13/28 ,  G06F13/10 ,  Y02D10/14

摘要： Described herein are methods and systems for virtualization of a USB device to enable sharing of the USB device among a plurality of host processors in a multi-processor computing system. A USB virtualization unit for sharing of the USB device include a per-host register unit, each corresponding to a host processor includes one or more of a host register interface, host data interface, configuration registers, and host control registers, configured to receive simultaneous requests from one or more host processors from amongst the plurality of host processors for the USB device. The USB virtualization unit also includes a pre-fetch direct memory access (DMA) configured to pre-fetch DMA descriptors associated with the requests to store in a buffer. The USB virtualization unit further includes an endpoint specific switching decision logic (ESL) configured to schedule data access based on the DMA descriptors from the host processor's local memory corresponding to each request.

摘要翻译： 这里描述了用于虚拟化USB设备以使得能够在多处理器计算系统中的多个主机处理器之间共享USB设备的方法和系统。 用于共享USB设备的USB虚拟化单元包括每主机寄存器单元，每个主机寄存器单元对应于主处理器，包括主机寄存器接口，主机数据接口，配置寄存器和主机控制寄存器中的一个或多个，被配置为同时接收 来自用于USB设备的多个主机处理器中的一个或多个主机处理器的请求。 USB虚拟化单元还包括预取直接存储器访问（DMA），其被配置为预取与存储在缓冲器中的请求相关联的DMA描述符。 USB虚拟化单元还包括端点特定切换判定逻辑（ESL），其被配置为基于来自对应于每个请求的主处理器的本地存储器的DMA描述符来调度数据访问。

公开(公告)号：US20140040382A1

公开(公告)日：2014-02-06

申请号：US14112393

申请日：2012-04-19

申请人： Balaji Kanigicherla ,  Siva Raghuram Voleti ,  Dhanumjai Pasumarthy

发明人： Balaji Kanigicherla ,  Siva Raghuram Voleti ,  Dhanumjai Pasumarthy

IPC分类号： H04L29/08

CPC分类号： G06F13/28 ,  G06F9/30047 ,  G06F9/30145 ,  G06F13/1673 ,  G06F13/38 ,  G06F13/385 ,  G06F13/387 ,  G06K7/0043 ,  G06K7/0052 ,  G06K7/0073 ,  G06K19/07741 ,  H04L67/10

摘要： Described herein are methods and system for virtualization of the secure digital (SD) host controller to enable sharing a SD device among various multiple host processors in a multi-processor computing system. In one implementation the method of sharing a SD device amongst a plurality of hosts of a multi-host computing system comprises detecting the SD device on occurrence of a reset event, receiving an enumeration request, from at least a first host and a second host of the plurality of hosts, to enumerate the SD device with respect to the second host, enumerating the SD device with respect to the second host, and initiating data exchange between the SD device and each of the plurality of hosts.

摘要翻译： 这里描述了用于安全数字（SD）主机控制器的虚拟化的方法和系统，以使得能够在多处理器计算系统中的各种多个主机处理器之间共享SD设备。 在一个实施方式中，在多主机计算系统的多个主机之间共享SD设备的方法包括：在发生复位事件的同时，从至少第一主机和第二主机接收枚举请求来检测SD设备 所述多个主机相对于所述第二主机枚举所述SD设备，针对所述第二主机枚举所述SD设备，以及启动所述SD设备与所述多个主机中的每一个之间的数据交换。

公开(公告)号：US20140032601A1

公开(公告)日：2014-01-30

申请号：US14111058

申请日：2012-04-09

申请人： Balaji Kanigicherla ,  Krishna Mohan Tandaboina ,  Siva Raghuram Voleti ,  Surya Narayana Dommeti ,  Sridhar Adusumilli

发明人： Balaji Kanigicherla ,  Krishna Mohan Tandaboina ,  Siva Raghuram Voleti ,  Surya Narayana Dommeti ,  Sridhar Adusumilli

IPC分类号： G06F17/30

CPC分类号： G06F17/30194 ,  G06F17/30165

摘要： File system sharing in multi-host computing system (100) running multiple operating systems is described herein. A file systems stored on different data partitions (110-1) and (110-1), of different operating systems (106-1) and (106-2), running on a multi-host computing system (100) may be shared based on file server-client architecture. According to the implementation, an operating system (106-1) may share its file system as file server and other operating system (106-2) may access the shared file system as file client. In one implementation, the sharing of data between multiple hosts is enabled by a dedicated high speed, low latency. inter processor communication bus, FiRE (124).

摘要翻译： 这里描述了运行多个操作系统的多主机计算系统（100）中的文件系统共享。 存储在多主机计算系统（100）上运行的不同操作系统（106-1）和（106-2）的不同数据分区（110-1）和（110-1））上的文件系统可以被共享 基于文件服务器 - 客户端架构。 根据该实现，操作系统（106-1）可以作为文件服务器共享其文件系统，并且其他操作系统（106-2）可以作为文件客户端访问共享文件系统。 在一个实现中，通过专用的高速度，低延迟来实现多个主机之间的数据共享。 处理器间通讯总线，FiRE（124）。

公开(公告)号：US20070258278A1

公开(公告)日：2007-11-08

申请号：US11418459

申请日：2006-05-05

申请人： Abdallah Bacha ,  Rainer Menes ,  Siva Raghuram

发明人： Abdallah Bacha ,  Rainer Menes ,  Siva Raghuram

IPC分类号： G11C5/02

CPC分类号： H05K1/181 ,  G11C5/04 ,  G11C8/12 ,  H05K2201/10159 ,  H05K2203/1572 ,  Y02P70/611

摘要： A memory module includes a first printed circuit board, wherein some of the memory chips in each of first and second ranks of memory chips are assembled on one side of the printed circuit board and others of the first and second ranks are assembled on the other side of the printed circuit board. First and second registers are respectively connected to the first and second address buses for respectively addressing the first and second ranks of memory chips. Since the addresses buses are separate for the two ranks, it is possible to activate only the address bus associated with the particular rank being addressed. In this manner, address activation power is saved by not activating the address bus of the other rank which is not addressed. Due to less power dissipation, it is possible to operate the memory module without a full DIMM heat spreader.

摘要翻译： 存储器模块包括第一印刷电路板，其中存储器芯片的第一和第二列中的每一个中的一些存储器芯片组装在印刷电路板的一侧上，并且第一和第二列的其它部分被组装在另一侧 的印刷电路板。 第一和第二寄存器分别连接到第一和第二地址总线，以分别寻址第一和第二等级的存储器芯片。 由于地址总线对于两个等级是分开的，所以可以仅激活与被寻址的特定等级相关联的地址总线。 以这种方式，通过不激活未被寻址的其他等级的地址总线来节省地址激活功率。 由于功耗较小，可以在没有全DIMM散热器的情况下操作内存模块。

公开(公告)号：US20070245072A1

公开(公告)日：2007-10-18

申请号：US11384837

申请日：2006-03-21

申请人： Siva Raghuram

发明人： Siva Raghuram

IPC分类号： G06F13/00

CPC分类号： G06F13/4243 ,  G11C5/00

摘要： Pre-switching of output signals of a register within a registered memory module is described herein. The register receives a plurality of signals at respective input terminals, and the register stores the input signals in response to transitions of a clock signal. The register further includes output terminals on which the stored input signals are present as high or low level output signals. The high and low level output signals of the output terminals are applied to a plurality of memory devices. The high and low level output signals, which are present on the output terminals, are pre-switched to intermediate level signals having a signal height greater than that of the low level output signal and less than that of the high level output signal. The pre-switching occurs between following transitions of the clock signal determined for storing the input signals.

摘要翻译： 本文描述了在注册的存储器模块内的寄存器的输出信号的预切换。 寄存器在相应的输入端接收多个信号，寄存器响应于时钟信号的转换来存储输入信号。 寄存器还包括存储的输入信号作为高电平或低电平输出信号的输出端子。 输出端子的高电平和低电平输出信号被施加到多个存储器件。 存在于输出端子上的高电平和低电平输出信号被预先切换到具有比低电平输出信号的信号高的信号高度并且小于高电平输出信号的信号高度的中间电平信号。 预切换发生在为存储输入信号而确定的时钟信号的以下转换之间。

公开(公告)号：US07266639B2

公开(公告)日：2007-09-04

申请号：US11010182

申请日：2004-12-10

申请人： Siva Raghuram

发明人： Siva Raghuram

IPC分类号： G06F12/00 ,  G11C8/06 ,  G11C8/12

CPC分类号： G11C5/04 ,  G11C8/12

摘要： The invention refers to a Memory Rank Decoder for a Multi-Rank Dual Inline Memory Module (DIMM) having a predetermined number of DRAM memory chips mounted on a printer circuit board (PCB), wherein each DRAM memory chip comprises a predetermined number of stacked DRAM memory dies which are selectable by a memory rank selection signal (r), wherein the memory rank decoder generates the memory rank selection signal (r) in response to external selection signals applied to the dual inline module (DIMM).

摘要翻译： 本发明涉及具有安装在打印机电路板（PCB）上的预定数量的DRAM存储器芯片的多级双列直插式存储器模块（DIMM）的存储器级别解码器，其中每个DRAM存储器芯片包括预定数量的堆叠DRAM 可由存储器等级选择信号（r）选择的存储器管芯，其中存储器级解码器响应于施加到双列直插模块（DIMM）的外部选择信号而产生存储器级选择信号（r）。

公开(公告)号：US20070091704A1

公开(公告)日：2007-04-26

申请号：US11437846

申请日：2006-05-19

申请人： Siva RaghuRam ,  Josef Schuster ,  Simon Muff ,  Abdallah Bacha

发明人： Siva RaghuRam ,  Josef Schuster ,  Simon Muff ,  Abdallah Bacha

IPC分类号： G11C7/00

CPC分类号： H05K1/181 ,  G11C5/04 ,  G11C5/063 ,  H05K2201/09409 ,  H05K2201/09418 ,  Y02P70/611

摘要： In a first embodiment, the invention provides a memory module having an electronic printed circuit board and a plurality of semiconductor chips of the same type that are mounted on at least one outer face of the printed circuit board. The printed circuit board has a connector strip, which runs at a first edge of the at least one outer face in a first direction and has a multiplicity of electrical contacts that are lined up in the first direction. The printed circuit board extends in the first direction between two opposite second edges. At least nine of the semiconductor chips of the same type are respectively mounted next to one another on the outer face of the printed circuit board between the center of the printed circuit board and the respective second edge of the printed circuit board. The semiconductor chips of the same type respectively have a smaller dimension and, in the direction perpendicular to the smaller dimension, a larger dimension that is larger than the smaller dimension. A respective first group of four of the semiconductor chips of the same type, which are oriented so as to have their shorter dimension parallel to the connector strip, is arranged at the respective second edge of the printed circuit board. A second group of five semiconductor chips of the same type is respectively arranged between the first group of semiconductor chips and the center of the printed circuit board. The first group of semiconductor chips and the second group of semiconductor chips are actuated by two separate line buses whose conductor tracks branch toward all the semiconductor chips in the respective group of semiconductor chips.

摘要翻译： 在第一实施例中，本发明提供一种具有电子印刷电路板和安装在印刷电路板的至少一个外表面上的相同类型的多个半导体芯片的存储模块。 印刷电路板具有一个连接器条，其在第一方向的至少一个外表面的第一边缘处延伸，并且具有在第一方向上排列的多个电触点。 印刷电路板沿第一方向在两个相对的第二边缘之间延伸。 在印刷电路板的中心和印刷电路板的相应第二边缘之间，相同类型的至少九个半导体芯片分别彼此相邻地安装在印刷电路板的外表面上。 相同类型的半导体芯片分别具有较小的尺寸，并且在垂直于较小尺寸的方向上具有大于较小尺寸的较大尺寸。 在印刷电路板的相应第二边缘处布置相同类型的四个半导体芯片的相应的第一组，其被定向成具有与连接器条平行的较短尺寸。 第一组相同类型的五个半导体芯片分别布置在第一组半导体芯片和印刷电路板的中心之间。 第一组半导体芯片和第二组半导体芯片由两条单独的线路总线驱动，其导体轨迹分支到相应的半导体芯片组中的所有半导体芯片。

公开(公告)号：US09189166B2

公开(公告)日：2015-11-17

申请号：US14111379

申请日：2012-04-09

申请人： Balaji Kanigicherla ,  Krishna Mohan Tandaboina ,  Siva Raghuram Voleti ,  Karamveer Yadav

发明人： Balaji Kanigicherla ,  Krishna Mohan Tandaboina ,  Siva Raghuram Voleti ,  Karamveer Yadav

IPC分类号： G06F3/06 ,  G06F13/12

CPC分类号： G06F3/0632 ,  G06F3/0625 ,  G06F3/067 ,  G06F13/126

摘要： Described herein is a system having a multi-host SATA controller (102) configured to provide communication and control between two or more independent host processors (104) and a single SATA device (108). In one implementation, the multi-host SATA controller (102) includes the device switching layer (206), the device control layer (208), the link layer (210), and the physical layer (212). The device switching layer (206) allows the host processors (104) to issue commands concurrently rather than in sequential order. For this, the device switching layer (206) has independent set of host device registers (214) corresponding to each of the host processors (104). The device switching layer (206) also has independent DMA engines (216) to perform a command pre-fetching from respective host system memories (105). Further, a command switch engine (220) may arbitrate commands in case both the host processors (104) wish to access the SATA device (108) simultaneously.

摘要翻译： 这里描述的是具有多主机SATA控制器（102）的系统，其被配置为提供两个或多个独立主机处理器（104）和单个SATA设备（108）之间的通信和控制。 在一个实现中，多主机SATA控制器（102）包括设备切换层（206），设备控制层（208），链路层（210）和物理层（212）。 设备切换层（206）允许主处理器（104）同时发布命令，而不是以顺序发布。 为此，设备切换层（206）具有对应于每个主处理器（104）的独立的主机设备寄存器集（214）。 设备切换层（206）还具有独立的DMA引擎（216），以执行从相应主机系统存储器（105）预取的命令。 此外，命令切换引擎（220）可以在主机处理器（104）希望同时访问SATA设备（108）的情况下仲裁命令。

公开(公告)号：US09047264B2

公开(公告)日：2015-06-02

申请号：US14111432

申请日：2012-04-09

申请人： Balaji Kanigicherla ,  Siva Raghuram Voleti ,  Rajani Lotti ,  Krishna Mohan Tandaboina

发明人： Balaji Kanigicherla ,  Siva Raghuram Voleti ,  Rajani Lotti ,  Krishna Mohan Tandaboina

IPC分类号： G06F13/28 ,  G06F13/24

CPC分类号： G06F13/24 ,  G06F13/28 ,  G06F2213/0038

摘要： Described herein is a system having a multi-host low pin count (LPC) controller (100) configured to facilitate sharing of common peripheral devices by multiple hosts (115) of a multi-host computing system (110). In one implementation, the multi-host LPC controller (100) interfaces with the hosts (115) via an ON-chip bus or an LPC-IN-chip bus. Further, the multi-host LPC controller (100) includes a LPC-IN controller (160) and a microcontroller (155) to moderate among requests generated by the hosts (115). The requests can be target accesses, DMA accesses, and BM accesses. Also, the multi-host LPC controller (100) is configured to operate in a software mode and an auto mode. Based on the mode the multi-host LPC controller (100) is operating in, the requests generated by the various hosts are moderated.

摘要翻译： 这里描述的是具有多主机低引脚数（LPC）控制器（100）的系统，其被配置为便于多主机计算系统（110）的多个主机（115）共享公共外围设备。 在一个实现中，多主机LPC控制器（100）经由片上总线或LPC-IN芯片总线与主机（115）接口。 此外，多主机LPC控制器（100）包括LPC-IN控制器（160）和微控制器（155），用于在由主机（115）生成的请求中进行调节。 请求可以是目标访问，DMA访问和BM访问。 此外，多主机LPC控制器（100）被配置为以软件模式和自动模式操作。 基于多主机LPC控制器（100）正在操作的模式，由各种主机产生的请求被调节。