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公开(公告)号：US07386696B2
公开(公告)日：2008-06-10
申请号：US10887019
申请日：2004-07-08
IPC分类号： G06F12/00
CPC分类号： G11C5/063
摘要： The invention relates to a semiconductor memory module having a plurality of memory chips arranged in at least one row and at least one buffer chip which drives and receives clock signals and command and address signals to the memory chips and data signals to and from the memory chips via a clock, address, command and data bus inside the module and which forms an interface to an external primary memory bus. The semiconductor memory module has an even number of buffer chips arranged on it and all of the memory chips are connected to two respective buffer chips at least by one signal line type from a signal group and just to one of the two buffer chips by the remaining signal lines from the group. The sum of the electrical signal propagation times for the actuating signals via their lines from one buffer chip to a respective one of the memory chips and the electrical signal propagation times for the data signals from this memory chip to the other buffer chip during the read operation is the same for all of the memory chips, and control means for controlling the respective data write and read operation to or from the memory chips are provided in order to drive the clock signals and command and address signals in the same respective direction as the data signals via the bus inside the module when data are being written and read.
摘要翻译： 本发明涉及一种半导体存储器模块，其具有布置在至少一行的多个存储器芯片和至少一个缓冲器芯片，该缓冲器芯片驱动并接收时钟信号，以及将命令和寻址信号存储到存储器芯片以及从存储器芯片传送数据信号 通过模块内的时钟，地址，命令和数据总线，并形成与外部主存储器总线的接口。 半导体存储器模块具有布置在其上的偶数个缓冲器芯片，并且所有存储器芯片至少通过一个信号线类型从信号组连接到两个相应的缓冲器芯片，并且仅剩下两个缓冲器芯片之一 来自该组的信号线。 在读取操作期间，通过其线从一个缓冲芯片到相应的一个存储器芯片的致动信号的电信号传播时间和从该存储器芯片到另一个缓冲器芯片的数据信号的电信号传播时间之和 对于所有存储器芯片是相同的，并且提供用于控制到存储器芯片或从存储器芯片的相应数据写入和读取操作的控制装置，以便以与数据相同的相同方向驱动时钟信号和命令和寻址信号 当数据被写入和读取时通过模块内的总线发送信号。
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公开(公告)号：US07224636B2
公开(公告)日：2007-05-29
申请号：US10890934
申请日：2004-07-14
IPC分类号： G11C8/00
CPC分类号： G11C29/028 , G11C5/063 , G11C29/50012
摘要： The invention relates to a semiconductor memory module having a plurality of memory chips arranged next to one another in a row. The memory module has a module-internal clock, command/address and data bus which transfers clock signal, command and address signals and also data signals from a memory controller device to the memory chips and data signals from the memory chips to the memory controller device. The memory module has respective clock, command/address and data signal lines. The clock signal lines comprise two differential clock signal lines which, at their end opposite to the memory controller device are either open or connected to one another by a short-circuiting bridge. The memory chips, during a write operation, synchronize the write data with the clock signal running from the memory controller device to the end of the clock signal line and, during a read operation, output the read data synchronously with the clock signal reflected from the open or short-circuited end of the clock signal lines.
摘要翻译： 本发明涉及一种半导体存储器模块，该半导体存储器模块具有彼此排成一列的多个存储器芯片。 存储器模块具有模块内部时钟，命令/地址和数据总线，其将时钟信号，命令和地址信号以及数据信号从存储器控制器设备传送到存储器芯片，并将数据信号从存储器芯片传送到存储器控制器设备 。 存储器模块具有各自的时钟，命令/地址和数据信号线。 时钟信号线包括两个差分时钟信号线，它们在其与存储器控制器装置相对的端部通过短路桥断开或彼此连接。 在写入操作期间，存储器芯片将写入数据与从存储器控制器设备运行到时钟信号线的时钟信号同步，并且在读取操作期间，与从该存储器控制器设备反射的时钟信号同步地输出读取数据 开路或短路的时钟信号线。
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公开(公告)号：US06972981B2
公开(公告)日：2005-12-06
申请号：US10909205
申请日：2004-07-30
IPC分类号： G11C5/06 , G11C7/22 , G11C11/4076
CPC分类号： G11C7/222 , G11C5/063 , G11C7/22 , G11C11/4076
摘要： The invention relates to a semiconductor memory module having a plurality of memory chips and at least one buffer chip, which drives clock signals and command and address signals to the memory chips and also drives data signals to, and receives them from, the memory chips via a module-internal clock, address, command and data signal bus. The buffer chip forms an interface to an external memory main bus and the memory chips are arranged in at least one row. The memory chips have separate writing and reading clock signal inputs for receiving the clock signals and the clock signal lines are routed in at least one loop, via the memory chips, from the buffer chip to the end of each row and from there back to the buffer chip
摘要翻译： 本发明涉及具有多个存储器芯片和至少一个缓冲芯片的半导体存储器模块，其驱动时钟信号并将命令和寻址信号传送到存储器芯片，并且还将数据信号驱动至存储器芯片并从存储器芯片接收它们，并经由 模块内部时钟，地址，命令和数据信号总线。 缓冲芯片形成与外部存储器主总线的接口，并且存储器芯片布置在至少一行中。 存储器芯片具有单独的写入和读取时钟信号输入，用于接收时钟信号，并且时钟信号线在至少一个循环中经由存储器芯片从缓冲器芯片路由到每行的末端，并且从那里返回到 缓冲芯片
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公开(公告)号：US20050038966A1
公开(公告)日：2005-02-17
申请号：US10850382
申请日：2004-05-21
CPC分类号： G11C7/10 , G06F13/1678
摘要： The present invention relates to a memory arrangement having a controller and having at least one memory device. Data signals, control signals and address signals can be transferred between the controller and the memory device. The memory arrangement is designed in such a way that the data signals can be transferred via data signal lines between the controller and the memory device. The memory arrangement is furthermore designed in such a way that the control signals and the address signals can likewise be transferred via the data signal lines between the controller and the memory device.
摘要翻译： 本发明涉及一种具有控制器并具有至少一个存储器件的存储器装置。 数据信号，控制信号和地址信号可以在控制器和存储器件之间传输。 存储器布置被设计成使得数据信号可以通过控制器和存储器件之间的数据信号线传送。 此外，存储器布置被设计成使得控制信号和地址信号同样能够经由控制器和存储器件之间的数据信号线传送。
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公开(公告)号：US07477717B2
公开(公告)日：2009-01-13
申请号：US10831001
申请日：2004-04-23
IPC分类号： H03M9/00
CPC分类号： H03M9/00
摘要： An input receiver circuit is provided for receiving a noisy high-speed input signal and for generating a plurality of output signals that can be processed at a low acquisition speed compared to the speed of the high-speed input signal. The input receiver circuit includes an input for receiving the high-speed input signal (data), a plurality of integration elements and a switch for connecting the input to one of the plurality of integration elements for integrating the high-speed input signal. The input receiver circuit further includes a plurality of means for receiving one of the integrated high-speed input signals at a time and for outputting one of the plurality of output signals at a time, and a controller for controlling the switch.
摘要翻译： 提供输入接收器电路，用于接收噪声高速输入信号并产生与高速输入信号的速度相比可以以低采集速度处理的多个输出信号。 输入接收电路包括用于接收高速输入信号（数据）的输入端，多个积分元件和用于将输入连接到多个积分元件中的一个用于积分高速输入信号的开关。 输入接收电路还包括多个用于一次接收集成高速输入信号之一并用于一次输出多个输出信号中的一个的装置，以及用于控制开关的控制器。
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公开(公告)号：US07376802B2
公开(公告)日：2008-05-20
申请号：US10850382
申请日：2004-05-21
CPC分类号： G11C7/10 , G06F13/1678
摘要： The present invention relates to a memory arrangement having a controller and having at least one memory device. Data signals, control signals and address signals can be transferred between the controller and the memory device. The memory arrangement is designed in such a way that the data signals can be transferred via data signal lines between the controller and the memory device. The memory arrangement is furthermore designed in such a way that the control signals and the address signals can likewise be transferred via the data signal lines between the controller and the memory device.
摘要翻译： 本发明涉及一种具有控制器并具有至少一个存储器件的存储器装置。 数据信号，控制信号和地址信号可以在控制器和存储器件之间传输。 存储器布置被设计成使得数据信号可以通过控制器和存储器件之间的数据信号线传送。 此外，存储器布置被设计成使得控制信号和地址信号同样能够经由控制器和存储器件之间的数据信号线传送。
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公开(公告)号：US20060248260A1
公开(公告)日：2006-11-02
申请号：US11392217
申请日：2006-03-29
申请人： Maksim Kuzmenka , Simon Muff , Hermann Ruckerbauer
发明人： Maksim Kuzmenka , Simon Muff , Hermann Ruckerbauer
IPC分类号： G06F12/02
CPC分类号： H03K19/018514 , H03K19/0175 , H03K19/01812
摘要： A circuit system includes a means for controlling a first and a second memory unit by means of a differential control signal. The differential control signal includes a first control signal and a second control signal, which is inverted to the first control signal. Further, the circuit system comprises a differential control signal line, which includes a first signal line for routing the first control signal and a second signal line for routing the second control signal. The first switching unit is connected via the first signal line and the second circuit unit is connected via the second signal line to the means for controlling.
摘要翻译： 电路系统包括用于通过差分控制信号控制第一和第二存储器单元的装置。 差分控制信号包括第一控制信号和第二控制信号，其被反转到第一控制信号。 此外，电路系统包括差分控制信号线，其包括用于路由第一控制信号的第一信号线和用于路由第二控制信号的第二信号线。 第一开关单元经由第一信号线连接，第二电路单元经由第二信号线连接到控制装置。
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公开(公告)号：US07061784B2
公开(公告)日：2006-06-13
申请号：US10886814
申请日：2004-07-08
IPC分类号： G11C5/06
CPC分类号： G11C11/4093 , G11C5/063 , G11C7/10
摘要： The invention relates to a semiconductor memory module having at least one memory chip and a buffer chip, which drives clock, address and command signals to the memory chip and drives data signals to, and receives them from, the memory chip via a module-internal clock, address, command and data bus. The buffer chip forms an interface to an external memory main bus. The data bus lines and/or the clock, command and address bus lines are respectively connected to the buffer chip at their two ends and are capable of being driven by the buffer chip from these two ends. Control means are being provided and set up in such a manner that they respectively match the directions of propagation of the data signals and of the clock, command and address signals on the corresponding bus lines during writing and reading.
摘要翻译： 本发明涉及一种具有至少一个存储器芯片和缓冲芯片的半导体存储器模块，其将时钟，地址和命令信号驱动到存储器芯片，并且经由模块内部驱动数据信号并从存储器芯片接收它们 时钟，地址，命令和数据总线。 缓冲芯片形成与外部存储器主总线的接口。 数据总线和/或时钟，命令和地址总线分别在两端分别连接到缓冲芯片，并且能够被这两端的缓冲芯片驱动。 正在提供和设置控制装置，使得它们在写入和读取期间它们分别匹配数据信号的传播方向以及相应总线上的时钟，命令和地址信号。
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公开(公告)号：US20060092715A1
公开(公告)日：2006-05-04
申请号：US11099222
申请日：2005-04-05
IPC分类号： G11C7/10
CPC分类号： G11C7/1084 , G11C7/1078 , G11C7/1093 , G11C7/14
摘要： A circuit exhibits a signal input, means for determining a reference level on the basis of properties of a signal received at the signal input. In addition, the circuit further exhibits means for evaluating the signal on the basis of the reference level.
摘要翻译： 电路呈现信号输入，用于基于在信号输入处接收的信号的特性来确定参考电平的装置。 此外，电路还具有用于基于参考电平来评估信号的装置。
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10.发明授权公开(公告)号：US06840808B2
公开(公告)日：2005-01-11
申请号：US10610241
申请日：2003-06-30
CPC分类号： H01R12/52 , H01R12/716
摘要： A connector is described for fixing a plurality of switching assemblies on a substrate. The connector is also for making contact with the plurality of switching assemblies, which have compatible interfaces. The connector has a plurality of receptacle devices with contact elements and internal contact connections between corresponding contact elements, as a result of which, the length of the connections between the switching assemblies is reduced, signal propagation times are shortened and a higher clock rate for operating the switching assemblies is made possible.
摘要翻译： 描述了用于将多个开关组件固定在基板上的连接器。 连接器还用于与具有兼容接口的多个开关组件接触。 连接器具有多个具有接触元件的插座装置和相应的接触元件之间的内部接触连接，其结果是，开关组件之间的连接长度减小，信号传播时间缩短，操作时钟频率更高 开关组件成为可能。
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