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公开(公告)号：US08183948B2
公开(公告)日：2012-05-22
申请号：US12702798
申请日：2010-02-09
申请人： Herschel A. Ainspan , John F. Bulzacchelli , Daniel J. Friedman , Ankush Goel , Alexander V. Rylyakov
发明人： Herschel A. Ainspan , John F. Bulzacchelli , Daniel J. Friedman , Ankush Goel , Alexander V. Rylyakov
CPC分类号： H03B5/1212 , H03B5/1215 , H03B5/1228 , H03B5/1253 , H03B5/1256 , H03B5/1265 , H03B2200/0088 , H03L7/099 , H03L7/10 , H03L7/18 , H03L2207/06 , H03L2207/50
摘要： A design for an oscillator, and a PLL incorporating such an oscillator, which takes up little physical area but maintains a large tuning range and low phase noise. Two LC-tanks are nested and switched. Through tuning the inactive tank, the range of the active tank may be increased and finer tuning becomes possible.
摘要翻译： 振荡器的设计，以及包含这种振荡器的PLL，其占用很小的物理面积，但保持较大的调谐范围和低的相位噪声。 两个LC坦克被嵌套和切换。 通过调节不活动的水箱，可以增加活动水箱的范围，并可以进行更精细的调节。
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公开(公告)号：US20110063038A1
公开(公告)日：2011-03-17
申请号：US12702798
申请日：2010-02-09
申请人： Herschel A. Ainspan , John F. Bulzacchelli , Daniel J. Friedman , Ankush Goel , Alexander V. Rylyakov
发明人： Herschel A. Ainspan , John F. Bulzacchelli , Daniel J. Friedman , Ankush Goel , Alexander V. Rylyakov
CPC分类号： H03B5/1212 , H03B5/1215 , H03B5/1228 , H03B5/1253 , H03B5/1256 , H03B5/1265 , H03B2200/0088 , H03L7/099 , H03L7/10 , H03L7/18 , H03L2207/06 , H03L2207/50
摘要： A design for an oscillator, and a PLL incorporating such an oscillator, which takes up little physical area but maintains a large tuning range and low phase noise. Two LC-tanks are nested and switched. Through tuning the inactive tank, the range of the active tank may be increased and finer tuning becomes possible.
摘要翻译： 振荡器的设计，以及包含这种振荡器的PLL，其占用很小的物理面积，但保持较大的调谐范围和低的相位噪声。 两个LC坦克被嵌套和切换。 通过调节不活动的水箱，可以增加活动水箱的范围，并可以进行更精细的调节。
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公开(公告)号：US08779865B2
公开(公告)日：2014-07-15
申请号：US13350981
申请日：2012-01-16
申请人： Herschel A. Ainspan , John F. Bulzacchelli , Daniel J. Friedman , Ankush Goel , Alexander V. Rylyakov
发明人： Herschel A. Ainspan , John F. Bulzacchelli , Daniel J. Friedman , Ankush Goel , Alexander V. Rylyakov
CPC分类号： H03B5/1212 , H03B5/1215 , H03B5/1228 , H03B5/1253 , H03B5/1256 , H03B5/1265 , H03B2200/0088 , H03L7/099 , H03L7/10 , H03L7/18 , H03L2207/06 , H03L2207/50
摘要： A design for an oscillator, and a PLL incorporating such an oscillator, which takes up little physical area but maintains a large tuning range and low phase noise. Two LC-tanks are nested and switched. Through tuning the inactive tank, the range of the active tank may be increased and finer tuning becomes possible.
摘要翻译： 振荡器的设计，以及包含这种振荡器的PLL，其占用很小的物理面积，但保持较大的调谐范围和低的相位噪声。 两个LC坦克被嵌套和切换。 通过调节不活动的水箱，可以增加活动水箱的范围，并可以进行更精细的调节。
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4.发明授权Optimal dithering of a digitally controlled oscillator with clock dithering for gain and bandwidth control 有权具有时钟抖动的数字控制振荡器的最佳抖动，用于增益和带宽控制公开(公告)号：US08138840B2
公开(公告)日：2012-03-20
申请号：US12358736
申请日：2009-01-23
申请人： Herschel A. Ainspan , John F. Bulzacchelli , Zeynep Toprak Deniz , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
发明人： Herschel A. Ainspan , John F. Bulzacchelli , Zeynep Toprak Deniz , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
摘要： A digital phase locked loop (DPLL) and method include an adjustable delay line configured to receive a reference clock as an input and to output a dithered reference clock signal. A phase and frequency detector (PFD) is configured to compare the dithered reference clock signal with a feedback clock signal to determine phase and frequency differences between the dithered reference clock signal and the feedback clock signal. A digitally controlled oscillator (DCO) is configured to receive early or late determinations from the PFD to adjust an output in accordance therewith, wherein the dithered reference clock signal distributes jitter response to enhance overall operation of the DPLL.
摘要翻译： 数字锁相环（DPLL）和方法包括可调延迟线，其配置为接收参考时钟作为输入并输出抖动参考时钟信号。 相位和频率检测器（PFD）被配置为将抖动参考时钟信号与反馈时钟信号进行比较，以确定抖动参考时钟信号和反馈时钟信号之间的相位和频率差。 数字控制振荡器（DCO）被配置为接收来自PFD的早期或晚期确定以根据其调整输出，其中抖动参考时钟信号分配抖动响应以增强DPLL的整体操作。
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5.发明申请OPTIMAL DITHERING OF A DIGITALLY CONTROLLED OSCILLATOR WITH CLOCK DITHERING FOR GAIN AND BANDWIDTH CONTROL 有权数字控制振荡器的最佳抖动，具有时钟抖动，用于增益和带宽控制公开(公告)号：US20100188158A1
公开(公告)日：2010-07-29
申请号：US12358736
申请日：2009-01-23
申请人： Herschel A. Ainspan , John F. Bulzacchelli , Zeynep Toprak Deniz , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
发明人： Herschel A. Ainspan , John F. Bulzacchelli , Zeynep Toprak Deniz , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
IPC分类号： H03L7/099
摘要： A digital phase locked loop (DPLL) and method include an adjustable delay line configured to receive a reference clock as an input and to output a dithered reference clock signal. A phase and frequency detector (PFD) is configured to compare the dithered reference clock signal with a feedback clock signal to determine phase and frequency differences between the dithered reference clock signal and the feedback clock signal. A digitally controlled oscillator (DCO) is configured to receive early or late determinations from the PFD to adjust an output in accordance therewith, wherein the dithered reference clock signal distributes jitter response to enhance overall operation of the DPLL.
摘要翻译： 数字锁相环（DPLL）和方法包括可调延迟线，其配置为接收参考时钟作为输入并输出抖动参考时钟信号。 相位和频率检测器（PFD）被配置为将抖动参考时钟信号与反馈时钟信号进行比较，以确定抖动参考时钟信号和反馈时钟信号之间的相位和频率差。 数字控制振荡器（DCO）被配置为接收来自PFD的早期或晚期确定以根据其调整输出，其中抖动参考时钟信号分配抖动响应以增强DPLL的整体操作。
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公开(公告)号：US08704567B2
公开(公告)日：2014-04-22
申请号：US13611008
申请日：2012-09-12
申请人： Herschel A. Ainspan , Mark A. Ferriss , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
发明人： Herschel A. Ainspan , Mark A. Ferriss , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
IPC分类号： H03L7/06
CPC分类号： H03L7/1072 , H03L7/087 , H03L7/089 , H03L7/093
摘要： Phase locked loop (PLL) architectures are provided such as hybrid PLL architectures having separate digital integrating control paths and analog proportional control paths. An analog proportional control path can be implemented with a charge pump circuit that includes resistors in series with CMOS switches to generate control currents (e.g., Up/Down control currents) which are used to adjust a control voltage applied to a digitally controlled oscillator. A digital integrating control path can be implemented with a series of sigma-delta modulators that operate at different frequencies to convert higher bit data signals to lower bit data signals along the digital integrating control path. A single phase frequency detector may be implemented to generate control signals that separately control the analog proportional and digital integrating control paths.
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7.发明申请公开(公告)号：US20100013531A1
公开(公告)日：2010-01-21
申请号：US12173140
申请日：2008-07-15
IPC分类号： H03L7/06
CPC分类号： H03L7/107 , H03L7/093 , H03L7/1075 , H03L2207/50
摘要： PLL (phase locked loop) circuits and methods are provided in which PWM (pulse width modulation) techniques are to achieve continuous fine tuning control of DCO (digitally controlled oscillator) circuits. In general, pulse width modulation techniques are applied to further modulate dithered control signals that are used to enhance the frequency tuning resolution of the DCO such that the dithered control signals are applied to the fractional tracking control port of the DCO for a selected fraction of a full clock signal based pulse width modulation applied.
摘要翻译： 提供PLL（锁相环）电路和方法，其中PWM（脉宽调制）技术将实现DCO（数字控制振荡器）电路的连续微调控制。 通常，应用脉冲宽度调制技术来进一步调制用于增强DCO的频率调谐分辨率的抖动控制信号，使得抖动控制信号被施加到DCO的分数跟踪控制端口，用于所选择的部分 采用全时钟信号脉冲宽度调制。
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8.发明授权Phase-locked loop circuits and methods implementing multiplexer circuit for fine tuning control of digitally controlled oscillators 失效锁相环电路和实现多路复用电路的方法，用于数字控制振荡器的微调控制公开(公告)号：US07750701B2
公开(公告)日：2010-07-06
申请号：US12173159
申请日：2008-07-15
IPC分类号： H03L7/06
CPC分类号： H03L7/093 , H03L7/099 , H03L7/107 , H03L2207/50
摘要： Circuits and methods are provided in which fine tuning control of a DCO (digitally controlled oscillator) circuit in a digital PLL circuit is realized by dither controlling a multiplexer circuit under digital control to selectively output one of a plurality of analog control voltages with varied voltage levels that are input to a fractional frequency control port of the DCO to drive tuning elements of the DCO at fractional frequency resolution and achieve continuous fine tuning of the DCO under analog control.
摘要翻译： 提供了电路和方法，其中数字PLL电路中的DCO（数字控制振荡器）电路的微调控制通过在数字控制下对多路复用器电路进行抖动控制来实现，以选择性地输出具有变化的电压电平的多个模拟控制电压中的一个 输入到DCO的分数频率控制端口，以分数频率分辨率驱动DCO的调谐元件，并在模拟控制下实现DCO的连续微调。
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公开(公告)号：US20130076449A1
公开(公告)日：2013-03-28
申请号：US13245409
申请日：2011-09-26
IPC分类号： H03L7/00
CPC分类号： H03L7/099 , H03L2207/50
摘要： Techniques for improved tuning control of varactor circuits are disclosed. For example, an apparatus comprises a plurality of varactors for tuning a frequency value. The plurality of varactors comprises approximately sqrt(2N) varactors, where N is a number of tunings steps and the plurality of varactors are respectively sized as 1x, 2x, 3x, 4x, . . . , approximately sqrt(2N)x, and where x is a unit of capacitance. A given one of the N tuning steps may be represented by more than one combination of varactors. This may be referred to as redundant numbering.
摘要翻译： 公开了用于改进变容二极管电路调谐控制的技术。 例如，一种装置包括用于调谐频率值的多个变容二极管。 多个变容二极管包括大约sqrt（2N）变容二极管，其中N是调谐步骤的数量，并且多个变容二极管分别尺寸为1x，2x，3x，4x。 。 。 ，约为sqrt（2N）x，其中x为电容单位。 N个调谐步骤中的给定一个可以由多个组合的变容二极管表示。 这可以称为冗余编号。
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10.发明授权Phase-locked loop circuits and methods implementing pulsewidth modulation for fine tuning control of digitally controlled oscillators 失效锁相环电路和实现脉冲宽度调制的方法，用于数字控制振荡器的微调控制公开(公告)号：US07772900B2
公开(公告)日：2010-08-10
申请号：US12173140
申请日：2008-07-15
IPC分类号： H03L7/06
CPC分类号： H03L7/107 , H03L7/093 , H03L7/1075 , H03L2207/50
摘要： PLL (phase locked loop) circuits and methods are provided in which PWM (pulse width modulation) techniques are to achieve continuous fine tuning control of DCO (digitally controlled oscillator) circuits. In general, pulse width modulation techniques are applied to further modulate dithered control signals that are used to enhance the frequency tuning resolution of the DCO such that the dithered control signals are applied to the fractional tracking control port of the DCO for a selected fraction of a full clock signal based pulse width modulation applied.
摘要翻译： 提供PLL（锁相环）电路和方法，其中PWM（脉宽调制）技术将实现DCO（数字控制振荡器）电路的连续微调控制。 通常，应用脉冲宽度调制技术来进一步调制用于增强DCO的频率调谐分辨率的抖动控制信号，使得抖动控制信号被施加到DCO的分数跟踪控制端口，用于所选择的部分 采用全时钟信号脉冲宽度调制。
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