公开(公告)号：US20230133270A1

公开(公告)日：2023-05-04

申请号：US17996136

申请日：2020-04-21

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： JEFFREY KEVIN JENSONNE ,  MASON GUNYUZLU

IPC: G06F8/654 ,  G06F9/4401

Abstract: In example implementations, a computing device is provided. The computing device includes a processor, a multiplexer, a first memory, a second memory, and a controller. The processor is to execute an operating system (OS). The multiplexer is coupled to the processor. The first memory is coupled to the multiplexer to store current basic input/output system (BIOS) instructions. The second memory is coupled to the multiplexer. The controller is coupled to the multiplexer to control connections of the multiplexer to allow the processor to store updated BIOS instructions in the second memory in a background while the OS is executed by processor.

公开(公告)号：US20230359553A1

公开(公告)日：2023-11-09

申请号：US18042673

申请日：2020-10-23

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： MASON GUNYUZLU ,  JEFFREY KEVIN JEANSONNE ,  KHOA HUYNH ,  THOMAS GEORGE SWANN

IPC: G06F12/02 ,  G06F12/0868 ,  G06F13/18 ,  G06F13/16

CPC classification number: G06F12/0246 ,  G06F12/0868 ,  G06F13/18 ,  G06F13/1689 ,  G06F2212/7201

Abstract: An electronic device is described that may include an integrated circuit, a volatile memory coupled to the integrated circuit, a non-volatile memory controller coupled to the integrated circuit, and a non-volatile memory coupled to the non-volatile memory controller. In some examples, the integrated circuit is to receive a first instruction at a first frequency via a first storage access physical interface and receive a second instruction at a second frequency via a second storage access physical interface, wherein the first instruction and the second instruction are volatile memory access instructions. The integrated circuit may also be to arbitrate access to the volatile memory based on the first instruction and the second instruction and, responsive to the access to the volatile memory, synchronize contents of the volatile memory with the non-volatile memory via the non-volatile memory controller to maintain data coherency between the volatile memory and the non-volatile memory.