公开(公告)号：US20080087951A1

公开(公告)日：2008-04-17

申请号：US11666461

申请日：2005-09-28

申请人： Hidefumi Takaya ,  Kimimori Hamada ,  Kyosuke Miyagi ,  Yasushi Okura ,  Akira Kuroyanagi ,  Norihiko Tokura

发明人： Hidefumi Takaya ,  Kimimori Hamada ,  Kyosuke Miyagi ,  Yasushi Okura ,  Akira Kuroyanagi ,  Norihiko Tokura

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/402 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7811

摘要： The invention has an object to provide an insulation gate type semiconductor device and a method for producing the same in which high breakdown voltage and compactness are achieved. The semiconductor device has a gate trench and a P floating region formed in the cell area and has a terminal trench and a P floating region formed in the terminal area. In addition, a terminal trench of three terminal trenches has a structure similar to that of the gate trench, and the other terminal trenches have a structure in which an insulation substance such as oxide silicon is filled. Also, the P floating region 51 is an area formed by implanting impurities from the bottom surface of the gate trench, and the P floating region is an area formed by implanting impurities from the bottom surface of the terminal trench.

摘要翻译： 本发明的目的是提供一种绝缘栅型半导体器件及其制造方法，其中实现了高的击穿电压和紧凑性。 半导体器件具有形成在单元区域中的栅极沟槽和P浮动区域，并且具有形成在端子区域中的端子沟槽和P浮动区域。 此外，三个端子沟槽的端子沟槽具有与栅极沟槽类似的结构，而另一个端子沟槽具有填充绝缘物质如氧化硅的结构。 此外，P浮动区域51是通过从栅极沟槽的底表面注入杂质形成的区域，并且P浮动区域是通过从端子沟槽的底表面注入杂质而形成的区域。

公开(公告)号：US08076718B2

公开(公告)日：2011-12-13

申请号：US11666461

申请日：2005-09-28

申请人： Hidefumi Takaya ,  Kimimori Hamada ,  Kyosuke Miyagi ,  Yasushi Okura ,  Akira Kuroyanagi ,  Norihito Tokura

发明人： Hidefumi Takaya ,  Kimimori Hamada ,  Kyosuke Miyagi ,  Yasushi Okura ,  Akira Kuroyanagi ,  Norihito Tokura

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/402 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7811

摘要： The invention has an object to provide an insulation gate type semiconductor device and a method for producing the same in which high breakdown voltage and compactness are achieved. The semiconductor device has a gate trench and a P floating region formed in the cell area and has a terminal trench and a P floating region formed in the terminal area. In addition, a terminal trench of three terminal trenches has a structure similar to that of the gate trench, and the other terminal trenches have a structure in which an insulation substance such as oxide silicon is filled. Also, the P floating region 51 is an area formed by implanting impurities from the bottom surface of the gate trench, and the P floating region is an area formed by implanting impurities from the bottom surface of the terminal trench.

摘要翻译： 本发明的目的是提供一种绝缘栅型半导体器件及其制造方法，其中实现了高的击穿电压和紧凑性。 半导体器件具有形成在单元区域中的栅极沟槽和P浮动区域，并且具有形成在端子区域中的端子沟槽和P浮动区域。 此外，三个端子沟槽的端子沟槽具有与栅极沟槽类似的结构，而另一个端子沟槽具有填充绝缘物质如氧化硅的结构。 此外，P浮动区域51是通过从栅极沟槽的底表面注入杂质形成的区域，并且P浮动区域是通过从端子沟槽的底表面注入杂质而形成的区域。

公开(公告)号：US07999312B2

公开(公告)日：2011-08-16

申请号：US12223871

申请日：2007-01-26

申请人： Hidefumi Takaya ,  Kimimori Hamada ,  Kyosuke Miyagi

发明人： Hidefumi Takaya ,  Kimimori Hamada ,  Kyosuke Miyagi

IPC分类号： H01L29/66 ,  H01L29/732 ,  H01L29/78 ,  H01L21/426

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7811

摘要： A semiconductor 100 has a P− body region and an N− drift region in the order from an upper surface side thereof. A gate trench and a terminal trench passing through the P− body region are formed. The respective trenches are surrounded with P diffusion regions at the bottom thereof. The gate trench builds a gate electrode therein. A P−− diffusion region, which is in contact with the end portion in a lengthwise direction of the gate trench and is lower in concentration than the P− body region and the P diffusion region, is formed. The P−− diffusion region is depleted prior to the P diffusion region when the gate voltage is off. The P−− diffusion region serves as a hole supply path to the P diffusion region when the gate voltage is on.

摘要翻译： 半导体100具有从其上表面侧开始的顺序的P-体区域和N-漂移区域。 形成通过P-体区域的栅极沟槽和端子沟槽。 各个沟槽在其底部被P扩散区包围。 栅极沟槽在其中形成栅电极。 形成了与栅极沟槽的长度方向上的端部接触并且浓度低于P体区域和P扩散区域的P扩散区域。 当栅极电压关闭时，P扩散区在P扩散区之前耗尽。 当栅极电压接通时，P扩散区域用作到P扩散区域的空穴供应路径。

公开(公告)号：US20100224932A1

公开(公告)日：2010-09-09

申请号：US12223871

申请日：2007-01-26

申请人： Hidefumi Takaya ,  Kimimori Hamada ,  Kyosuke Miyagi

发明人： Hidefumi Takaya ,  Kimimori Hamada ,  Kyosuke Miyagi

IPC分类号： H01L29/78 ,  H01L21/265

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7811

摘要： A semiconductor 100 has a P− body region and an N− drift region in the order from an upper surface side thereof. A gate trench and a terminal trench passing through the P− body region are formed. The respective trenches are surrounded with P diffusion regions at the bottom thereof. The gate trench builds a gate electrode therein. A P−− diffusion region, which is in contact with the end portion in a lengthwise direction of the gate trench and is lower in concentration than the P− body region and the P diffusion region, is formed. The P−− diffusion region is depleted prior to the P diffusion region when the gate voltage is off. The P−− diffusion region serves as a hole supply path to the P diffusion region when the gate voltage is on.

摘要翻译： 半导体100具有从其上表面侧开始的顺序的P-体区域和N-漂移区域。 形成通过P-体区域的栅极沟槽和端子沟槽。 各个沟槽在其底部被P扩散区包围。 栅极沟槽在其中形成栅电极。 形成了与栅极沟槽的长度方向上的端部接触并且浓度低于P体区域和P扩散区域的P扩散区域。 当栅极电压关闭时，P扩散区在P扩散区之前耗尽。 当栅极电压接通时，P扩散区域用作到P扩散区域的空穴供应路径。

公开(公告)号：US09190503B2

公开(公告)日：2015-11-17

申请号：US14347897

申请日：2011-09-28

申请人： Masaru Senoo ,  Kyosuke Miyagi ,  Tsuyoshi Nishiwaki ,  Jun Saito

发明人： Masaru Senoo ,  Kyosuke Miyagi ,  Tsuyoshi Nishiwaki ,  Jun Saito

IPC分类号： H01L29/66 ,  H01L29/739 ,  H01L29/36 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

CPC分类号： H01L29/66348 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/6634 ,  H01L29/7396 ,  H01L29/7397

摘要： An IGBT has an emitter region, a top body region that is formed below the emitter region, a floating region that is formed below the top body region, a bottom body region that is formed below the floating region, a trench, a gate insulating film that covers an inner face of the trench, and a gate electrode that is arranged inside the trench. When a distribution of a concentration of p-type impurities in the top body region and the floating region, which are located below the emitter region, is viewed along a thickness direction of a semiconductor substrate, the concentration of the p-type impurities decreases as a downward distance increases from an upper end of the top body region that is located below the emitter region, and assumes a local minimum value at a predetermined depth in the floating region.

摘要翻译： IGBT具有发射极区域，形成在发射极区域下方的顶部主体区域，形成在顶部主体区域下方的浮动区域，形成在浮动区域下方的底部区域，沟槽，栅极绝缘膜 覆盖沟槽的内表面和布置在沟槽内的栅电极。 当沿着半导体衬底的厚度方向观察位于发射极区域下方的顶体区域和浮动区域中的p型杂质浓度的分布时，p型杂质的浓度随着 向下的距离从位于发射极区域下方的顶部主体区域的上端增加，并且在浮动区域中在预定深度处呈现局部最小值。

公开(公告)号：US20140231866A1

公开(公告)日：2014-08-21

申请号：US14347897

申请日：2011-09-28

申请人： Masaru Senoo ,  Kyosuke Miyagi ,  Tsuyoshi Nishiwaki ,  Jun Saito

发明人： Masaru Senoo ,  Kyosuke Miyagi ,  Tsuyoshi Nishiwaki ,  Jun Saito

IPC分类号： H01L29/739 ,  H01L29/66

CPC分类号： H01L29/66348 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/6634 ,  H01L29/7396 ,  H01L29/7397

摘要： An IGBT has an emitter region, a top body region that is formed below the emitter region, a floating region that is formed below the top body region, a bottom body region that is formed below the floating region, a trench, a gate insulating film that covers an inner face of the trench, and a gate electrode that is arranged inside the trench. When a distribution of a concentration of p-type impurities in the top body region and the floating region, which are located below the emitter region, is viewed along a thickness direction of a semiconductor substrate, the concentration of the p-type impurities decreases as a downward distance increases from an upper end of the top body region that is located below the emitter region, and assumes a local minimum value at a predetermined depth in the floating region.

摘要翻译： IGBT具有发射极区域，形成在发射极区域下方的顶部主体区域，形成在顶部主体区域下方的浮动区域，形成在浮动区域下方的底部区域，沟槽，栅极绝缘膜 覆盖沟槽的内表面和布置在沟槽内的栅电极。 当沿着半导体衬底的厚度方向观察位于发射极区域下方的顶体区域和浮动区域中的p型杂质浓度的分布时，p型杂质的浓度随着 向下的距离从位于发射极区域下方的顶部主体区域的上端增加，并且在浮动区域中在预定深度处呈现局部最小值。