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公开(公告)号：US08705492B2
公开(公告)日：2014-04-22
申请号：US13386112
申请日：2011-06-06
申请人： Hidekuni Yomo , Kiyotaka Kobayashi
发明人： Hidekuni Yomo , Kiyotaka Kobayashi
CPC分类号： H04L25/03318 , H04B7/0697 , H04B7/086 , H04L25/0204 , H04L25/0232 , H04L25/03171 , H04L25/03891 , H04L25/03955 , H04L2025/03426
摘要： A MIMO receiving apparatus that can demodulate a spatially multiplexed signal without using any division operation requiring a large quantity of operation resources. In the MIMO receiving apparatus, stream separation section (105) separates a spatially multiplexed signal into a plurality of streams based on numerator submatrix A. Numerator submatrix A is determined according to channel matrix H and a canceller scheme and corresponds to a numerator of stream separation matrix S that equalizes the phase and amplitude of the spatially multiplexed signal. Denominator part calculation section (108) calculates a denominator (denominator coefficient) of stream separation matrix S and correction section (117) corrects a threshold determined according to a modulation scheme of the spatially multiplexed signal using the denominator (denominator coefficient) of stream separation matrix S. Demapping sections (109-1 to 109-3) calculate likelihoods of the plurality of streams through a threshold decision using the corrected threshold.
摘要翻译： 一种MIMO接收装置，其可以在不需要大量操作资源的任何划分操作的情况下解调空间复用信号。 在MIMO接收装置中，流分离部（105）基于分子子矩阵A将空间复用信号分离为多个流。根据信道矩阵H和消除方案确定分子子矩阵A，并对应于流分离的分子 矩阵S，其均衡空间复用信号的相位和幅度。 分母部分计算部分（108）计算流分离矩阵S的分母（分母系数），校正部分（117）使用流分离矩阵的分母（分母系数）校正根据空间复用信号的调制方案确定的阈值 映射部分（109-1至109-3）通过使用校正的阈值的阈值判定来计算多个流的似然性。
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公开(公告)号：US20120127889A1
公开(公告)日：2012-05-24
申请号：US13386112
申请日：2011-06-06
申请人： Hidekuni Yomo , Kiyotaka Kobayashi
发明人： Hidekuni Yomo , Kiyotaka Kobayashi
CPC分类号： H04L25/03318 , H04B7/0697 , H04B7/086 , H04L25/0204 , H04L25/0232 , H04L25/03171 , H04L25/03891 , H04L25/03955 , H04L2025/03426
摘要： A MIMO receiving apparatus that can demodulate a spatially multiplexed signal without using any division operation requiring a large quantity of operation resources. In the MIMO receiving apparatus, stream separation section (105) separates a spatially multiplexed signal into a plurality of streams based on numerator submatrix A. Numerator submatrix A is determined according to channel matrix H and a canceller scheme and corresponds to a numerator of stream separation matrix S that equalizes the phase and amplitude of the spatially multiplexed signal. Denominator part calculation section (108) calculates a denominator (denominator coefficient) of stream separation matrix S and correction section (117) corrects a threshold determined according to a modulation scheme of the spatially multiplexed signal using the denominator (denominator coefficient) of stream separation matrix S. Demapping sections (109-1 to 109-3) calculate likelihoods of the plurality of streams through a threshold decision using the corrected threshold.
摘要翻译： 一种MIMO接收装置，其可以在不需要大量操作资源的任何划分操作的情况下解调空间复用信号。 在MIMO接收装置中，流分离部（105）基于分子子矩阵A将空间复用信号分离为多个流。根据信道矩阵H和消除方案确定分子子矩阵A，并对应于流分离的分子 矩阵S，其均衡空间复用信号的相位和幅度。 分母部分计算部分（108）计算流分离矩阵S的分母（分母系数），校正部分（117）使用流分离矩阵的分母（分母系数）校正根据空间复用信号的调制方案确定的阈值 映射部分（109-1至109-3）通过使用校正的阈值的阈值判定来计算多个流的似然性。
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公开(公告)号：US20130223265A1
公开(公告)日：2013-08-29
申请号：US13881292
申请日：2011-10-26
IPC分类号： H04W72/04
CPC分类号： H04W72/0446 , H04B1/0003 , H04B1/406 , H04W88/06
摘要： The present invention provides a communication processor that is compatible with a plurality of communication protocols and also limits increases in circuit scale. A communication processor (200) comprises a computational processing circuit resource (270) having a plurality of programmable computation units (FU: Function Unit). An operation mode determination unit (230) determines an operation mode indicating a communication protocol application state. A permitted processing time determination unit (240) determines a permitted processing time in accordance with the determined operation mode. A resource allocation unit (250), in accordance with the permitted processing time, divides the plurality of FUs and allocates computational resources for each communication protocol indicated by the operation mode. A region controller (260) controls the allocated computation resources. The computational processing circuit resource (270) outputs data from after the computational processing at the timing when the computation processing ends.
摘要翻译： 本发明提供了一种与多种通信协议兼容的通信处理器，并且还限制了电路规模的增加。 通信处理器（200）包括具有多个可编程计算单元（FU：功能单元）的计算处理电路资源（270）。 操作模式确定单元（230）确定指示通信协议应用状态的操作模式。 允许处理时间确定单元（240）根据确定的操作模式确定允许的处理时间。 资源分配单元（250）根据允许的处理时间对多个FU进行分割，并为由操作模式指示的每个通信协议分配计算资源。 区域控制器（260）控制所分配的计算资源。 计算处理电路资源（270）在计算处理结束的定时从计算处理之后输出数据。
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公开(公告)号：US20120236926A1
公开(公告)日：2012-09-20
申请号：US13158295
申请日：2011-06-10
IPC分类号： H04L27/01
CPC分类号： H04L25/03159
摘要： A circuit for adaptive feedback equalization is disclosed. In one aspect, the circuit includes a frequency-domain feedforward filtering section and a feedback filtering section, a slicer to slice a block of equalized symbols, a summing module for summing outputs of the filtering sections thereby yielding the block of equalized symbols. First and second updating modules provide coefficient updates to the filtering sections. The updating modules are fed with a frequency-domain converted block of error signals indicating the difference between the block of equalized symbols at the slicer input and the block of sliced symbols at the slicer output and for computing updates using the frequency-domain converted block of error signals. A time-domain compensation module receives a time-domain version of the updated filter coefficients of the feedback filtering section and symbols of the block of sliced symbols. It adds a feedback error compensation signal to the block of equalized symbols.
摘要翻译： 公开了一种用于自适应反馈均衡的电路。 在一个方面中，电路包括频域前馈滤波部分和反馈滤波部分，用于对均衡符号块进行切片的切片器，用于对滤波部分的输出进行求和从而产生均衡符号块的求和模块。 第一和第二更新模块向过滤部分提供系数更新。 更新模块被馈送有频域转换的误差信号块，其指示限幅器输入处的均衡符号块与限幅器输出处的分片符号块之间的差异，并且使用频域转换的块来计算更新 错误信号。 时域补偿模块接收反馈滤波部分的更新的滤波器系数的时域版本和分片符号块的符号。 它向均衡符号块添加反馈误差补偿信号。
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公开(公告)号：US20100091910A1
公开(公告)日：2010-04-15
申请号：US12527654
申请日：2008-02-20
IPC分类号： H04L27/06
CPC分类号： H03M13/27 , H04J11/003 , H04L1/005 , H04L1/0071 , H04L27/2626 , H04L27/2647
摘要： Provided is a reception device which can reduce a parallel interference canceller processing delay. The reception device (200) includes: a plurality of reception antennas (210A, 210B); an address generation unit (2332) which converts the write-in or read-out order of channel estimation values according to a predetermined rearrangement rule; a channel estimation storage unit (2334) which writes in channel estimation values in the converted order; an address generation unit (2338) which converts the data sequence write-in or read-out order according to the rearrangement rule; a signal storage unit (2340) which writes in or reads out data sequences in the converted order; a replica generation unit (2336) which generates a replica signal by re-modulating the data sequence according to the channel estimation value; a cancel unit (2342) which successively extracts a channel estimation value and a data sequence and generates a stream signal in which the data sequence interference signal is cancelled, by using the channel estimation value, the data sequence, and the replica signal; and an error correction decoding unit (2350) which corrects and decodes an error according to the stream signal.
摘要翻译： 提供一种可以减少并行干扰消除器处理延迟的接收装置。 接收装置（200）包括：多个接收天线（210A，210B）; 地址生成单元，根据预定的重排规则转换信道估计值的写入或读出顺序; 以转换顺序写入信道估计值的信道估计存储单元（2334） 根据重排规则转换数据序列写入或读出顺序的地址生成单元（2338）; 信号存储单元（2340），其以转换的顺序写入或读出数据序列; 复制生成单元，其通过根据所述信道估计值重新调制所述数据序列来生成复制信号; 取消单元（2342），其通过使用信道估计值，数据序列和复制信号，连续地提取信道估计值和数据序列，并生成数据序列干扰信号被消除的流信号; 以及根据流信号校正和解码错误的纠错解码单元（2350）。
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公开(公告)号：US09301297B2
公开(公告)日：2016-03-29
申请号：US13881292
申请日：2011-10-26
CPC分类号： H04W72/0446 , H04B1/0003 , H04B1/406 , H04W88/06
摘要： A communication processor that is compatible with a plurality of communication protocols while limiting increases in circuit scale is provided. The communication processor includes a computational processing circuit resource having a plurality of programmable function units (FUs). An operation mode determination unit determines an operation mode indicating a communication protocol application state. A permitted processing time determination unit determines a permitted processing time in accordance with the determined operation mode. In accordance with the permitted processing time, a resource allocation unit divides the plurality of FUs and allocates computational resources for each communication protocol indicated by the operation mode. A region controller controls the allocated computation resources. The computational processing circuit resource outputs data from after the computational processing at the timing when the computation processing ends.
摘要翻译： 提供了在限制电路规模增加的同时与多个通信协议兼容的通信处理器。 通信处理器包括具有多个可编程功能单元（FU）的计算处理电路资源。 操作模式确定单元确定指示通信协议应用状态的操作模式。 允许处理时间确定单元根据确定的操作模式确定允许的处理时间。 根据允许的处理时间，资源分配单元对多个FU进行划分，并为由操作模式指示的每个通信协议分配计算资源。 区域控制器控制分配的计算资源。 计算处理电路资源在计算处理结束的定时从计算处理之后输出数据。
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公开(公告)号：US08265206B2
公开(公告)日：2012-09-11
申请号：US12667579
申请日：2008-07-03
IPC分类号： H04L27/08
CPC分类号： H04L1/0048 , H04L1/0025 , H04L1/005 , H04L1/06 , H04L25/0204 , H04L25/0224 , H04L25/03006 , H04L25/03171
摘要： A radio receiver which performs iterative decoding of a received signal is provided. The radio receiver comprises: a receiving unit receiving a signal on a symbol-by-symbol basis; a demodulation unit (303) demodulating the received signal; a last symbol timing generation unit (308) generating a last symbol timing signal on the basis of the signal demodulated by the demodulation unit (303); a modulation unit (304) modulating the signal demodulated by the demodulation unit (303); and a cancellation unit (306) cancelling an interference component of the received signal using a replica signal generated on the basis of the signal modulated by the modulation unit (304). The modulation unit (304) controls the timing of rearrangement of a data sequence on the basis of the timing of the last symbol. Thus, a radio receiver in which the receiving processing time is reduced can be provided.
摘要翻译： 提供对接收信号执行迭代解码的无线电接收机。 无线电接收机包括：接收单元，以符号为单位接收信号; 解调单元（303），对接收到的信号进行解调; 最后符号定时生成单元，基于由解调单元解调的信号生成最后的符号定时信号; 调制单元（304），调制由解调单元（303）解调的信号; 以及消除单元（306），使用基于由调制单元（304）调制的信号生成的复制信号来消除接收信号的干扰分量。 调制单元（304）基于最后一个符号的定时来控制数据序列的重排的定时。 因此，可以提供其中接收处理时间减少的无线电接收机。
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公开(公告)号：US08233571B2
公开(公告)日：2012-07-31
申请号：US12527654
申请日：2008-02-20
IPC分类号： H03D1/00
CPC分类号： H03M13/27 , H04J11/003 , H04L1/005 , H04L1/0071 , H04L27/2626 , H04L27/2647
摘要： A reception device includes reception antennas and an address generation unit that converts a write-in or read-out order of channel estimation values according to a rearrangement rule. A storage unit writes in or reads out channel estimation values in the converted order, and an address generation unit converts a data sequence write-in or read-out order according to the rearrangement rule. A signal storage unit writes in or reads out data sequences in the converted order, and a replica generation unit generates a replica signal by re-modulating the data sequence according to the channel estimation value. A cancel unit successively generates a stream signal in which a data sequence interference signal is cancelled, by using the channel estimation value, the data sequence, and the replica signal.
摘要翻译： 接收装置包括接收天线和地址生成单元，其根据重排规则转换信道估计值的写入或读出次序。 存储单元以转换的顺序写入或读出信道估计值，地址生成单元根据重排规则转换数据序列写入或读出顺序。 信号存储单元以转换的顺序写入或读出数据序列，并且副本生成单元通过根据信道估计值重新调制数据序列来生成复制信号。 取消单元通过使用信道估计值，数据序列和复制信号，依次生成数据序列干扰信号被消除的流信号。
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公开(公告)号：US08494035B2
公开(公告)日：2013-07-23
申请号：US13158295
申请日：2011-06-10
CPC分类号： H04L25/03159
摘要： A circuit for adaptive feedback equalization is disclosed. In one aspect, the circuit includes a frequency-domain feedforward filtering section and a feedback filtering section, a slicer to slice a block of equalized symbols, a summing module for summing outputs of the filtering sections thereby yielding the block of equalized symbols. First and second updating modules provide coefficient updates to the filtering sections. The updating modules are fed with a frequency-domain converted block of error signals indicating the difference between the block of equalized symbols at the slicer input and the block of sliced symbols at the slicer output and for computing updates using the frequency-domain converted block of error signals. A time-domain compensation module receives a time-domain version of the updated filter coefficients of the feedback filtering section and symbols of the block of sliced symbols. It adds a feedback error compensation signal to the block of equalized symbols.
摘要翻译： 公开了一种用于自适应反馈均衡的电路。 在一个方面中，电路包括频域前馈滤波部分和反馈滤波部分，用于对均衡符号块进行切片的切片器，用于对滤波部分的输出进行求和从而产生均衡符号块的求和模块。 第一和第二更新模块向过滤部分提供系数更新。 更新模块被馈送有频域转换的误差信号块，其指示限幅器输入处的均衡符号块与限幅器输出处的分片符号块之间的差异，并且使用频域转换的块来计算更新 错误信号。 时域补偿模块接收反馈滤波部分的更新的滤波器系数的时域版本和分片符号块的符号。 它向均衡符号块添加反馈误差补偿信号。
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公开(公告)号：US09154347B2
公开(公告)日：2015-10-06
申请号：US14239973
申请日：2012-06-29
CPC分类号： H04L25/03159 , G06F17/142 , H04L25/03057 , H04L27/01 , H04L2025/03414 , H04L2025/03541
摘要： An adaptive equalizer capable of suppressing an increase in circuit scale and an increase in operation clock frequency. An adaptive equalizer (100) performs an adaptive equalization process on a time-region signal in a frequency region. A signal converter (200) has: a first wide-bit memory (201) capable of reading/writing a plurality of sample signals; a first register group (202) comprising a plurality of registers capable of accessing the first wide-bit memory (201); a butterfly computation unit group (204) comprising a plurality of butterfly computation units; and a first connection switching unit (203) for switching the state of connection between the plurality of registers and the plurality of butterfly computation units.
摘要翻译： 一种自适应均衡器，其能够抑制电路规模的增加和操作时钟频率的增加。 自适应均衡器（100）对频率区域中的时域信号执行自适应均衡处理。 信号转换器（200）具有：能够读取/写入多个采样信号的第一宽位存储器（201） 第一寄存器组（202），包括能够访问第一宽位存储器（201）的多个寄存器; 蝴蝶计算单元组（204），包括多个蝶形计算单元; 以及用于切换多个寄存器与多个蝶形运算单元之间的连接状态的第一连接切换单元（203）。
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