公开(公告)号：US07422934B2

公开(公告)日：2008-09-09

申请号：US11465360

申请日：2006-08-17

申请人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Koji Ono ,  Toru Takayama

发明人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Koji Ono ,  Toru Takayama

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L29/4908 ,  H01L27/124 ,  H01L27/1288 ,  H01L27/32 ,  H01L27/3244 ,  H01L27/3246 ,  H01L27/3262 ,  H01L29/42384 ,  H01L29/66757 ,  H01L29/78621 ,  H01L51/5284 ,  H01L2029/7863

摘要： There is provided an inexpensive light emitting device and an electronic instrument using the same. In this invention, photolithography steps relating to manufacture of a transistor are reduced, so that the yield of the light emitting device is improved and the manufacturing period thereof is shortened. A feature is that a gate electrode is formed of conductive films of plural layers, and by using the selection ratio of those at the time of etching, the concentration of an impurity region formed in an active layer is adjusted.

摘要翻译： 提供了廉价的发光装置和使用它的电子仪器。 在本发明中，与晶体管的制造有关的光刻步骤减少，从而提高了发光器件的产量，并缩短了其制造周期。 特征在于，栅电极由多层导电膜形成，通过使用蚀刻时的选择比，调节在有源层中形成的杂质区域的浓度。

公开(公告)号：US07151015B2

公开(公告)日：2006-12-19

申请号：US09852672

申请日：2001-05-11

申请人： Hideomi Suzawa ,  Koji Ono ,  Toru Takayama ,  Tatsuya Arao ,  Shunpei Yamazaki

发明人： Hideomi Suzawa ,  Koji Ono ,  Toru Takayama ,  Tatsuya Arao ,  Shunpei Yamazaki

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L27/124 ,  H01L21/32136 ,  H01L27/1214 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627 ,  H01L29/78684 ,  H01L2029/7863

摘要： There has been a problem that the manufacturing process is complicated and the number of processes is increased when a TFT with an LDD structure or a TFT with a GOLD structure is formed. In a method of manufacturing a semiconductor device, after low concentration impurity regions (24, 25) are formed in a second doping process, a width of the low concentration impurity region which is overlapped with the third electrode (18c) and a width of the low concentration impurity region which is not overlapped with the third electrode can be freely controlled by a fourth etching process. Thus, in a region overlapped with the third electrode, a relaxation of electric field concentration is achieved and then a hot carrier injection can be prevented. And, in the region which is not overlapped with the third electrode, the off-current value can be suppressed.

摘要翻译： 当形成具有LDD结构的TFT或具有GOLD结构的TFT时，存在制造过程复杂并且处理次数增加的问题。 在制造半导体器件的方法中，在第二掺杂工艺中形成低浓度杂质区（24,25）之后，与第三电极（18c）重叠的低浓度杂质区的宽度和 可以通过第四蚀刻工艺来自由地控制不与第三电极重叠的低浓度杂质区域。 因此，在与第三电极重叠的区域中，实现电场浓度的松弛，然后可以防止热载流子注入。 并且，在不与第三电极重叠的区域中，可以抑制截止电流值。

公开(公告)号：US20070272989A1

公开(公告)日：2007-11-29

申请号：US11752437

申请日：2007-05-23

申请人： Hideomi Suzawa ,  Koji Ono ,  Toru Takayama

发明人： Hideomi Suzawa ,  Koji Ono ,  Toru Takayama

IPC分类号： H01L29/78

CPC分类号： H01L29/66757 ,  H01L27/1214 ,  H01L27/1259 ,  H01L27/127 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66598 ,  H01L29/78621 ,  H01L2029/7863

摘要： In the fabrication of semiconductor devices such as active matrix displays, the need to pattern resist masks in photolithography increases the number of steps in the fabrication process and the time required to complete them and consequently represents a substantial cost. This invention provides a method for forming an impurity region in a semiconductor layer 303 by doping an impurity element into the semiconductor layer self-aligningly using as a mask the upper layer (a second conducting film 306) of a gate electrode formed in two layers. The impurity element is doped into the semiconductor layer through the lower layer of the gate electrode (a first conducting film 305), and through a gate insulating film 304. By this means, an LDD region 313 of a GOLD structure is formed in the semiconductor layer 303.

摘要翻译： 在诸如有源矩阵显示器的半导体器件的制造中，在光刻中对抗蚀剂掩模进行图案化的需要增加了制造工艺中的步骤数量和完成它们所需的时间，因此代表了大量成本。 本发明提供了一种用于在半导体层中以自对准的方式将杂质元素掺杂到半导体层303中以形成两层栅电极的上层（第二导电膜306）作为掩模来形成杂质区的方法。 杂质元素通过栅电极（第一导电膜305）的下层，并通过栅极绝缘膜304掺杂到半导体层中。 通过这种方式，在半导体层303中形成GOLD结构的LDD区域313。

公开(公告)号：US20050040403A1

公开(公告)日：2005-02-24

申请号：US10960015

申请日：2004-10-08

申请人： Hideomi Suzawa ,  Koji Ono ,  Toru Takayama

发明人： Hideomi Suzawa ,  Koji Ono ,  Toru Takayama

IPC分类号： H01L21/30 ,  H01L21/336 ,  H01L29/49 ,  H01L29/786 ,  H01L29/04

CPC分类号： H01L29/66757 ,  H01L27/1214 ,  H01L27/1259 ,  H01L27/127 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66598 ,  H01L29/78621 ,  H01L2029/7863

摘要： In the fabrication of semiconductor devices such as active matrix displays, the need to pattern resist masks in photolithography increases the number of steps in the fabrication process and the time required to complete them and consequently represents a substantial cost. This invention provides a method for forming an impurity region in a semiconductor layer 303 by doping an impurity element into the semiconductor layer self-aligningly using as a mask the upper layer (a second conducting film 306) of a gate electrode formed in two layers. The impurity element is doped into the semiconductor layer through the lower layer of the gate electrode (a first conducting film 305), and through a gate insulating film 304. By this means, an LDD region 313 of a GOLD structure is formed in the semiconductor layer 303.

摘要翻译： 在诸如有源矩阵显示器的半导体器件的制造中，在光刻中对抗蚀剂掩模进行图案化的需要增加了制造工艺中的步骤数量和完成它们所需的时间，因此代表了大量成本。 本发明提供了一种用于在半导体层中以自对准的方式将杂质元素掺杂到半导体层303中以形成两层栅电极的上层（第二导电膜306）作为掩模来形成杂质区的方法。 杂质元素通过栅电极的下层（第一导电膜305）掺杂到半导体层中，并通过栅极绝缘膜304掺杂。通过这种方式，在半导体中形成GOLD结构的LDD区域313 层303。

公开(公告)号：US07589382B2

公开(公告)日：2009-09-15

申请号：US11752437

申请日：2007-05-23

申请人： Hideomi Suzawa ,  Koji Ono ,  Toru Takayama

发明人： Hideomi Suzawa ,  Koji Ono ,  Toru Takayama

IPC分类号： H01L29/94

CPC分类号： H01L29/66757 ,  H01L27/1214 ,  H01L27/1259 ,  H01L27/127 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66598 ,  H01L29/78621 ,  H01L2029/7863

摘要： In the fabrication of semiconductor devices such as active matrix displays, the need to pattern resist masks in photolithography increases the number of steps in the fabrication process and the time required to complete them and consequently represents a substantial cost. This invention provides a method for forming an impurity region in a semiconductor layer 303 by doping an impurity element into the semiconductor layer self-aligningly using as a mask the upper layer (a second conducting film 306) of a gate electrode formed in two layers. The impurity element is doped into the semiconductor layer through the lower layer of the gate electrode (a first conducting film 305), and through a gate insulating film 304. By this means, an LDD region 313 of a GOLD structure is formed in the semiconductor layer 303.

摘要翻译： 在诸如有源矩阵显示器的半导体器件的制造中，在光刻中对抗蚀剂掩模进行图案化的需要增加了制造工艺中的步骤数量和完成它们所需的时间，因此代表了大量成本。 本发明提供了一种用于在半导体层中以自对准的方式将杂质元素掺杂到半导体层303中以形成两层栅电极的上层（第二导电膜306）作为掩模来形成杂质区的方法。 杂质元素通过栅电极的下层（第一导电膜305）掺杂到半导体层中，并通过栅极绝缘膜304掺杂。通过这种方式，在半导体中形成GOLD结构的LDD区域313 层303。

公开(公告)号：US20070004157A1

公开(公告)日：2007-01-04

申请号：US11465360

申请日：2006-08-17

申请人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Koji Ono ,  Toru Takayama

发明人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Koji Ono ,  Toru Takayama

IPC分类号： H01L21/336

CPC分类号： H01L29/4908 ,  H01L27/124 ,  H01L27/1288 ,  H01L27/32 ,  H01L27/3244 ,  H01L27/3246 ,  H01L27/3262 ,  H01L29/42384 ,  H01L29/66757 ,  H01L29/78621 ,  H01L51/5284 ,  H01L2029/7863

摘要： There is provided an inexpensive light emitting device and an electronic instrument using the same. In this invention, photolithography steps relating to manufacture of a transistor are reduced, so that the yield of the light emitting device is improved and the manufacturing period thereof is shortened. A feature is that a gate electrode is formed of conductive films of plural layers, and by using the selection ratio of those at the time of etching, the concentration of an impurity region formed in an active layer is adjusted.

摘要翻译： 提供了廉价的发光装置和使用它的电子仪器。 在本发明中，与晶体管的制造有关的光刻步骤减少，从而提高了发光器件的产量，并缩短了其制造周期。 特征在于，栅电极由多层导电膜形成，通过使用蚀刻时的选择比，调节在有源层中形成的杂质区域的浓度。

公开(公告)号：US06773996B2

公开(公告)日：2004-08-10

申请号：US09852282

申请日：2001-05-10

申请人： Hideomi Suzawa ,  Koji Ono ,  Toru Takayama

发明人： Hideomi Suzawa ,  Koji Ono ,  Toru Takayama

IPC分类号： H01L21336

CPC分类号： H01L29/66757 ,  H01L27/1214 ,  H01L27/1259 ,  H01L27/127 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66598 ,  H01L29/78621 ,  H01L2029/7863

摘要： In the fabrication of semiconductor devices such as active matrix displays, the need to pattern resist masks in photolithography increases the number of steps in the fabrication process and the time required to complete them and consequently represents a substantial cost. This invention provides a method for forming an impurity region in a semiconductor layer 303 by doping an impurity element into the semiconductor layer self-aligningly using as a mask the upper,layer (a second conducting film 306) of a gate electrode formed in two layers. The impurity element is doped into the semiconductor layer through the lower layer of the gate electrode (a first conducting film 305), and through a gate insulating film 304. By this means, an LDD region 313 of a GOLD structure is formed in the semiconductor layer 303.

摘要翻译： 在诸如有源矩阵显示器的半导体器件的制造中，在光刻中对抗蚀剂掩模进行图案化的需要增加了制造工艺中的步骤数量和完成它们所需的时间，因此代表了大量成本。 本发明提供了一种用于在半导体层中以自对准的方式将杂质元素掺杂到半导体层303中以形成两层的栅电极的上层（第二导电膜306）作为掩模来形成杂质区的方法， 。 杂质元素通过栅电极的下层（第一导电膜305）掺杂到半导体层中，并通过栅极绝缘膜304掺杂。通过这种方式，在半导体中形成GOLD结构的LDD区域313 层303。

公开(公告)号：US08470647B2

公开(公告)日：2013-06-25

申请号：US11620576

申请日：2007-01-05

申请人： Hideomi Suzawa ,  Koji Ono ,  Toru Takayama ,  Tatsuya Arao ,  Shunpei Yamazaki

发明人： Hideomi Suzawa ,  Koji Ono ,  Toru Takayama ,  Tatsuya Arao ,  Shunpei Yamazaki

IPC分类号： H01L21/84

CPC分类号： H01L27/124 ,  H01L21/32136 ,  H01L27/1214 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627 ,  H01L29/78684 ,  H01L2029/7863

摘要： There has been a problem that the manufacturing process is complicated and the number of processes is increased when a TFT with an LDD structure or a TFT with a GOLD structure is formed. In a method of manufacturing a semiconductor device, after low concentration impurity regions (24, 25) are formed in a second doping process, a width of the low concentration impurity region which is overlapped with the third electrode (18c) and a width of the low concentration impurity region which is not overlapped with the third electrode can be freely controlled by a fourth etching process. Thus, in a region overlapped with the third electrode, a relaxation of electric field concentration is achieved and then a hot carrier injection can be prevented. And, in the region which is not overlapped with the third electrode, the off-current value can be suppressed.

摘要翻译： 当形成具有LDD结构的TFT或具有GOLD结构的TFT时，存在制造过程复杂并且处理次数增加的问题。 在制造半导体器件的方法中，在第二掺杂工艺中形成低浓度杂质区（24,25）之后，与第三电极（18c）重叠的低浓度杂质区的宽度和 不与第三电极重叠的低浓度杂质区域可以通过第四蚀刻工艺自由地控制。 因此，在与第三电极重叠的区域中，实现电场浓度的松弛，然后可以防止热载流子注入。 并且，在不与第三电极重叠的区域中，可以抑制截止电流值。

公开(公告)号：US07365750B2

公开(公告)日：2008-04-29

申请号：US11426138

申请日：2006-06-23

申请人： Shunpei Yamazaki ,  Jun Koyama ,  Yasuyuki Arai ,  Hideomi Suzawa ,  Koji Ono ,  Toru Takayama

发明人： Shunpei Yamazaki ,  Jun Koyama ,  Yasuyuki Arai ,  Hideomi Suzawa ,  Koji Ono ,  Toru Takayama

IPC分类号： G06K9/00

CPC分类号： G06K9/0004 ,  G07C9/00158 ,  H04M1/673 ,  H04M1/72519

摘要： It is an object to provide an user identity authentication system and an user identity authentication method with the Internet and a mobile information communication device. The mobile information communication device includes a liquid crystal device with a built-in image sensor. The image sensor reads individual information of a user, and user's identity is authenticated based on the individual information. A result of the authentication is unicast via the Internet. Alternatively, it is judged whether or not the result of the authentication is required to be unicast in accordance with a degree of requirement preset in the mobile information communication device or a destination terminal of communication, and the result is unicast via the Internet only when needed.

摘要翻译： 本发明的目的是提供一种用户身份认证系统和用户身份认证方法与因特网和移动信息通信设备。 移动信息通信装置包括具有内置图像传感器的液晶装置。 图像传感器读取用户的个人信息，并且基于个人信息认证用户的身份。 认证的结果是通过互联网进行单播。 或者，根据在移动信息通信装置或通信目的地终端中预先设定的要求，判定认证结果是否需要单播，并且结果仅在需要时通过因特网单播 。

公开(公告)号：US06933184B2

公开(公告)日：2005-08-23

申请号：US10622584

申请日：2003-07-21

申请人： Tatsuya Arao ,  Hideomi Suzawa ,  Koji Ono ,  Toru Takayama

发明人： Tatsuya Arao ,  Hideomi Suzawa ,  Koji Ono ,  Toru Takayama

IPC分类号： H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786

CPC分类号： H01L27/1259 ,  H01L27/1214 ,  H01L27/127 ,  H01L29/42384 ,  H01L29/78621 ,  H01L29/78627 ,  H01L2029/7863

摘要： Conventionally, when a TFT provided with an LDD structure or a TFT provided with a GOLD structure is to be formed, there is a problem in that the manufacturing process becomes complicated, which leads to the increase in the number of steps. An electrode formed of a lamination of a first conductive layer (18b) and a second conductive layer (17c), which have different widths from each other, is formed. After the first conductive layer (18b) is selectively etched to form a first conductive layer (18c), a low concentration impurity region (25a) overlapping the first conductive layer (18c) and a low concentration impurity region (25b) not overlapping the first conductive layer 18c are formed by doping an impurity element at a low concentration.

摘要翻译： 通常，当形成设置有LDD结构的TFT或具有GOLD结构的TFT时，存在制造过程变得复杂的问题，导致步骤数增加。 形成由彼此具有不同宽度的第一导电层（18b）和第二导电层（17c）的叠层形成的电极。 在选择性蚀刻第一导电层（18b）以形成第一导电层（18c）之后，与第一导电层（18c）和低浓度杂质区域（25b）重叠的低浓度杂质区域（25a） ）不是通过以低浓度掺杂杂质元素形成第一导电层18c。