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    Semiconductor device and manufacturing method thereof
    1.
    发明授权
    Semiconductor device and manufacturing method thereof 有权
    半导体装置及其制造方法

    公开(公告)号：US07151015B2

    公开(公告)日：2006-12-19

    申请号：US09852672

    申请日：2001-05-11

    申请人： Hideomi Suzawa ,  Koji Ono ,  Toru Takayama ,  Tatsuya Arao ,  Shunpei Yamazaki

    发明人： Hideomi Suzawa ,  Koji Ono ,  Toru Takayama ,  Tatsuya Arao ,  Shunpei Yamazaki

    IPC分类号： H01L21/00 ,  H01L21/84

    CPC分类号： H01L27/124 ,  H01L21/32136 ,  H01L27/1214 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627 ,  H01L29/78684 ,  H01L2029/7863

    摘要： There has been a problem that the manufacturing process is complicated and the number of processes is increased when a TFT with an LDD structure or a TFT with a GOLD structure is formed. In a method of manufacturing a semiconductor device, after low concentration impurity regions (24, 25) are formed in a second doping process, a width of the low concentration impurity region which is overlapped with the third electrode (18c) and a width of the low concentration impurity region which is not overlapped with the third electrode can be freely controlled by a fourth etching process. Thus, in a region overlapped with the third electrode, a relaxation of electric field concentration is achieved and then a hot carrier injection can be prevented. And, in the region which is not overlapped with the third electrode, the off-current value can be suppressed.

    摘要翻译： 当形成具有LDD结构的TFT或具有GOLD结构的TFT时，存在制造过程复杂并且处理次数增加的问题。 在制造半导体器件的方法中，在第二掺杂工艺中形成低浓度杂质区（24,25）之后，与第三电极（18c）重叠的低浓度杂质区的宽度和 可以通过第四蚀刻工艺来自由地控制不与第三电极重叠的低浓度杂质区域。 因此，在与第三电极重叠的区域中，实现电场浓度的松弛，然后可以防止热载流子注入。 并且，在不与第三电极重叠的区域中，可以抑制截止电流值。

    Semiconductor device and manufacturing method thereof
    2.
    发明授权
    Semiconductor device and manufacturing method thereof 有权
    半导体装置及其制造方法

    公开(公告)号：US08470647B2

    公开(公告)日：2013-06-25

    申请号：US11620576

    申请日：2007-01-05

    申请人： Hideomi Suzawa ,  Koji Ono ,  Toru Takayama ,  Tatsuya Arao ,  Shunpei Yamazaki

    发明人： Hideomi Suzawa ,  Koji Ono ,  Toru Takayama ,  Tatsuya Arao ,  Shunpei Yamazaki

    IPC分类号： H01L21/84

    CPC分类号： H01L27/124 ,  H01L21/32136 ,  H01L27/1214 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627 ,  H01L29/78684 ,  H01L2029/7863

    摘要： There has been a problem that the manufacturing process is complicated and the number of processes is increased when a TFT with an LDD structure or a TFT with a GOLD structure is formed. In a method of manufacturing a semiconductor device, after low concentration impurity regions (24, 25) are formed in a second doping process, a width of the low concentration impurity region which is overlapped with the third electrode (18c) and a width of the low concentration impurity region which is not overlapped with the third electrode can be freely controlled by a fourth etching process. Thus, in a region overlapped with the third electrode, a relaxation of electric field concentration is achieved and then a hot carrier injection can be prevented. And, in the region which is not overlapped with the third electrode, the off-current value can be suppressed.

    摘要翻译： 当形成具有LDD结构的TFT或具有GOLD结构的TFT时，存在制造过程复杂并且处理次数增加的问题。 在制造半导体器件的方法中，在第二掺杂工艺中形成低浓度杂质区（24,25）之后，与第三电极（18c）重叠的低浓度杂质区的宽度和 不与第三电极重叠的低浓度杂质区域可以通过第四蚀刻工艺自由地控制。 因此，在与第三电极重叠的区域中，实现电场浓度的松弛，然后可以防止热载流子注入。 并且，在不与第三电极重叠的区域中，可以抑制截止电流值。

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    3.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
    半导体器件及其制造方法

    公开(公告)号：US20070111424A1

    公开(公告)日：2007-05-17

    申请号：US11620576

    申请日：2007-01-05

    申请人： Hideomi Suzawa ,  Koji Ono ,  Toru Takayama ,  Tatsuya Arao ,  Shunpei Yamazaki

    发明人： Hideomi Suzawa ,  Koji Ono ,  Toru Takayama ,  Tatsuya Arao ,  Shunpei Yamazaki

    IPC分类号： H01L21/8238

    CPC分类号： H01L27/124 ,  H01L21/32136 ,  H01L27/1214 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627 ,  H01L29/78684 ,  H01L2029/7863

    摘要： There has been a problem that the manufacturing process is complicated and the number of processes is increased when a TFT with an LDD structure or a TFT with a GOLD structure is formed. In a method of manufacturing a semiconductor device, after low concentration impurity regions (24, 25) are formed in a second doping process, a width of the low concentration impurity region which is overlapped with the third electrode (18c) and a width of the low concentration impurity region which is not overlapped with the third electrode can be freely controlled by a fourth etching process. Thus, in a region overlapped with the third electrode, a relaxation of electric field concentration is achieved and then a hot carrier injection can be prevented. And, in the region which is not overlapped with the third electrode, the off-current value can be suppressed.

    摘要翻译： 当形成具有LDD结构的TFT或具有GOLD结构的TFT时，存在制造过程复杂并且处理次数增加的问题。 在制造半导体器件的方法中，在第二掺杂工艺中形成低浓度杂质区（24,25）之后，与第三电极（18c）重叠的低浓度杂质区的宽度和 可以通过第四蚀刻工艺来自由地控制不与第三电极重叠的低浓度杂质区域。 因此，在与第三电极重叠的区域中，实现电场浓度的松弛，然后可以防止热载流子注入。 并且，在不与第三电极重叠的区域中，可以抑制截止电流值。

    Semiconductor device and manufacturing method thereof
    4.
    发明授权
    Semiconductor device and manufacturing method thereof 有权
    半导体装置及其制造方法

    公开(公告)号：US07161177B2

    公开(公告)日：2007-01-09

    申请号：US10833080

    申请日：2004-04-28

    申请人： Hideomi Suzawa ,  Koji Ono ,  Toru Takayama ,  Tatsuya Arao ,  Shunpei Yamazaki

    发明人： Hideomi Suzawa ,  Koji Ono ,  Toru Takayama ,  Tatsuya Arao ,  Shunpei Yamazaki

    IPC分类号： H01L29/04 ,  H01L31/0376

    CPC分类号： H01L27/124 ,  H01L21/32136 ,  H01L27/1214 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627 ,  H01L29/78684 ,  H01L2029/7863

    摘要： There has been a problem that the manufacturing process is complicated and the number of processes is increased when a TFT with an LDD structure or a TFT with a GOLD structure is formed. In a method of manufacturing a semiconductor device, after low concentration impurity regions (24, 25) are formed in a second doping process, a width of the low concentration impurity region which is overlapped with the third electrode (18c) and a width of the low concentration impurity region which is not overlapped with the third electrode can be freely controlled by a fourth etching process. Thus, in a region overlapped with the third electrode, a relaxation of electric field concentration is achieved and then a hot carrier injection can be prevented. And, in the region which is not overlapped with the third electrode, the off-current value can be suppressed.

    摘要翻译： 当形成具有LDD结构的TFT或具有GOLD结构的TFT时，存在制造过程复杂并且处理次数增加的问题。 在制造半导体器件的方法中，在第二掺杂工艺中形成低浓度杂质区（24,25）之后，与第三电极（18c）重叠的低浓度杂质区的宽度和 可以通过第四蚀刻工艺来自由地控制不与第三电极重叠的低浓度杂质区域。 因此，在与第三电极重叠的区域中，实现电场浓度的松弛，然后可以防止热载流子注入。 并且，在不与第三电极重叠的区域中，可以抑制截止电流值。

    Method of manufacturing semiconductor device
    6.
    发明授权
    Method of manufacturing semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US06933184B2

    公开(公告)日：2005-08-23

    申请号：US10622584

    申请日：2003-07-21

    申请人： Tatsuya Arao ,  Hideomi Suzawa ,  Koji Ono ,  Toru Takayama

    发明人： Tatsuya Arao ,  Hideomi Suzawa ,  Koji Ono ,  Toru Takayama

    IPC分类号： H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786

    CPC分类号： H01L27/1259 ,  H01L27/1214 ,  H01L27/127 ,  H01L29/42384 ,  H01L29/78621 ,  H01L29/78627 ,  H01L2029/7863

    摘要： Conventionally, when a TFT provided with an LDD structure or a TFT provided with a GOLD structure is to be formed, there is a problem in that the manufacturing process becomes complicated, which leads to the increase in the number of steps. An electrode formed of a lamination of a first conductive layer (18b) and a second conductive layer (17c), which have different widths from each other, is formed. After the first conductive layer (18b) is selectively etched to form a first conductive layer (18c), a low concentration impurity region (25a) overlapping the first conductive layer (18c) and a low concentration impurity region (25b) not overlapping the first conductive layer 18c are formed by doping an impurity element at a low concentration.

    摘要翻译： 通常，当形成设置有LDD结构的TFT或具有GOLD结构的TFT时，存在制造过程变得复杂的问题，导致步骤数增加。 形成由彼此具有不同宽度的第一导电层（18b）和第二导电层（17c）的叠层形成的电极。 在选择性蚀刻第一导电层（18b）以形成第一导电层（18c）之后，与第一导电层（18c）和低浓度杂质区域（25b）重叠的低浓度杂质区域（25a） ）不是通过以低浓度掺杂杂质元素形成第一导电层18c。