公开(公告)号：US08390318B2

公开(公告)日：2013-03-05

申请号：US13401052

申请日：2012-02-21

申请人： Hideyuki Yokou ,  Takanori Eguchi ,  Manabu Ishimatsu

发明人： Hideyuki Yokou ,  Takanori Eguchi ,  Manabu Ishimatsu

IPC分类号： H03K17/16

CPC分类号： G11C29/022 ,  G11C29/028

摘要： Disclosed herein is a device that includes a replica buffer circuit that drives a calibration terminal, a reference-potential generating circuit that generates a reference potential, a comparison circuit that compares a potential appearing at the calibration terminal with the reference potential, and a control circuit that changes an output impedance of the replica buffer circuit based on a result of a comparison by the comparison circuit. The reference-potential generating circuit includes a first potential generating unit activated in response to an enable signal and a second potential generating unit activated regardless of the enable signal, and an output node of the first potential generating unit and an output node of the second potential generating unit are commonly connected to the comparison circuit.

摘要翻译： 本文公开了一种装置，其包括驱动校准端子的复制缓冲电路，产生参考电位的基准电位产生电路，将校准端子出现的电位与参考电位进行比较的比较电路和控制电路 其基于比较电路的比较结果来改变复制缓冲电路的输出阻抗。 参考电位产生电路包括响应于使能信号而被激活的第一电位产生单元和与使能信号无关地激活的第二电位产生单元，以及第一电位产生单元的输出节点和第二电位的输出节点 发电单元通常连接到比较电路。

公开(公告)号：US20120212254A1

公开(公告)日：2012-08-23

申请号：US13401052

申请日：2012-02-21

申请人： Hideyuki YOKOU ,  Takanori Eguchi ,  Manabu Ishimatsu

发明人： Hideyuki YOKOU ,  Takanori Eguchi ,  Manabu Ishimatsu

IPC分类号： H03K19/003

CPC分类号： G11C29/022 ,  G11C29/028

摘要： Disclosed herein is a device that includes a replica buffer circuit that drives a calibration terminal, a reference-potential generating circuit that generates a reference potential, a comparison circuit that compares a potential appearing at the calibration terminal with the reference potential, and a control circuit that changes an output impedance of the replica buffer circuit based on a result of a comparison by the comparison circuit. The reference-potential generating circuit includes a first potential generating unit activated in response to an enable signal and a second potential generating unit activated regardless of the enable signal, and an output node of the first potential generating unit and an output node of the second potential generating unit are commonly connected to the comparison circuit.

摘要翻译： 本文公开了一种装置，其包括驱动校准端子的复制缓冲电路，产生参考电位的基准电位产生电路，将校准端子出现的电位与参考电位进行比较的比较电路和控制电路 其基于比较电路的比较结果来改变复制缓冲电路的输出阻抗。 参考电位产生电路包括响应于使能信号而被激活的第一电位产生单元和与使能信号无关地激活的第二电位产生单元，以及第一电位产生单元的输出节点和第二电位的输出节点 发电单元通常连接到比较电路。

公开(公告)号：US08498831B2

公开(公告)日：2013-07-30

申请号：US12923831

申请日：2010-10-08

申请人： Akira Ide ,  Hideyuki Yoko ,  Kayoko Shibata ,  Kenichi Tanamachi ,  Takanori Eguchi ,  Yasuyuki Shigezane ,  Naoki Ogawa ,  Kazuo Hidaka

发明人： Akira Ide ,  Hideyuki Yoko ,  Kayoko Shibata ,  Kenichi Tanamachi ,  Takanori Eguchi ,  Yasuyuki Shigezane ,  Naoki Ogawa ,  Kazuo Hidaka

IPC分类号： G06F19/00

CPC分类号： G11C29/02 ,  G11C5/04 ,  G11C29/025 ,  H01L2224/16 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

摘要： To include one or a plurality of internal signal lines that electrically connects an interface chip to a core chip. The interface chip includes a first circuit that outputs a current to an internal wiring and the core chip includes a second circuit that outputs a current to the first internal signal line. The interface chip includes a determination circuit that has a first input terminal connected to the internal wiring through which the current outputted by the first circuit flows and a second input terminal connected to an end of the first internal signal line in the interface chip, and outputs a voltage according to a potential difference between a voltage of the first input terminal and a voltage of the second input terminal.

摘要翻译： 包括将接口芯片电连接到核心芯片的一个或多个内部信号线。 接口芯片包括将电流输出到内部布线的第一电路，并且芯片芯片包括向第一内部信号线输出电流的第二电路。 接口芯片包括确定电路，其具有连接到由第一电路输出的电流流过的内部布线的第一输入端子和连接到接口芯片中的第一内部信号线的一端的第二输入端子，并且输出 根据第一输入端子的电压与第二输入端子的电压之间的电位差的电压。

公开(公告)号：US20110093224A1

公开(公告)日：2011-04-21

申请号：US12923831

申请日：2010-10-08

申请人： Akira Ide ,  Hideyuki Yoko ,  Kayoko Shibata ,  Kenichi Tanamachi ,  Takanori Eguchi ,  Yasuyuki Shigezane ,  Naoki Ogawa ,  Kazuo Hidaka

发明人： Akira Ide ,  Hideyuki Yoko ,  Kayoko Shibata ,  Kenichi Tanamachi ,  Takanori Eguchi ,  Yasuyuki Shigezane ,  Naoki Ogawa ,  Kazuo Hidaka

IPC分类号： G01R19/00 ,  G06F19/00

CPC分类号： G11C29/02 ,  G11C5/04 ,  G11C29/025 ,  H01L2224/16 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

摘要： To include one or a plurality of internal signal lines that electrically connects an interface chip to a core chip. The interface chip includes a first circuit that outputs a current to an internal wiring and the core chip includes a second circuit that outputs a current to the first internal signal line. The interface chip includes a determination circuit that has a first input terminal connected to the internal wiring through which the current outputted by the first circuit flows and a second input terminal connected to an end of the first internal signal line in the interface chip, and outputs a voltage according to a potential difference between a voltage of the first input terminal and a voltage of the second input terminal.

摘要翻译： 包括将接口芯片电连接到核心芯片的一个或多个内部信号线。 接口芯片包括将电流输出到内部布线的第一电路，并且芯片芯片包括向第一内部信号线输出电流的第二电路。 接口芯片包括确定电路，其具有连接到由第一电路输出的电流流过的内部布线的第一输入端子和连接到接口芯片中的第一内部信号线的一端的第二输入端子，并且输出 根据第一输入端子的电压与第二输入端子的电压之间的电位差的电压。