公开(公告)号：US08665008B2

公开(公告)日：2014-03-04

申请号：US13398711

申请日：2012-02-16

申请人： Hideyuki Yokou ,  Isao Nakamura ,  Manabu Ishimatsu

发明人： Hideyuki Yokou ,  Isao Nakamura ,  Manabu Ishimatsu

IPC分类号： G05F1/10

CPC分类号： H02M1/00 ,  H02M7/003 ,  H03K19/00361

摘要： Disclosed herein is a device that includes a bias line to which a bias current flows, a switch circuit controlling an amount of the bias current based on a control signal, a control line to which the control signal is supplied, and a cancellation circuit substantially cancelling a potential fluctuation of the bias line caused by changing the control signal, the potential fluctuation propagating via a parasitic capacitance between the control line and the bias line.

摘要翻译： 本文公开了一种装置，其包括偏置电流流过的偏置线，基于控制信号控制偏置电流量的开关电路，提供控制信号的控制线以及基本取消的取消电路 通过改变控制信号引起的偏置线的电位波动，通过控制线和偏置线之间的寄生电容传播的电位波动。

公开(公告)号：US06504770B2

公开(公告)日：2003-01-07

申请号：US10067231

申请日：2002-02-07

申请人： Goro Kitsukawa ,  Toshitsugu Ueda ,  Manabu Ishimatsu ,  Michihiro Mishima

发明人： Goro Kitsukawa ,  Toshitsugu Ueda ,  Manabu Ishimatsu ,  Michihiro Mishima

IPC分类号： G11C700

CPC分类号： G11C29/80 ,  G11C29/81 ,  G11C29/814 ,  H01L27/105 ,  H01L27/10897

摘要： There is provided a semiconductor memory which allows a redundant memory cell to be disposed at the center while maintaining the continuity of layout units of direct peripheral circuits and allows the total yield of the memory cell and the direct peripheral circuits to be improved. The inventive semiconductor memory is a 64 M-bits or 256 M-bits DRAM using a hierarchical word line structure or a multi-division bit line structure and comprises a main row decoder region, a main word driver region, a column decoder region, a peripheral circuit/bonding pad region, a memory cell array, a sense amplifier region, a sub-word driver region, intersection regions and the like formed on one semiconductor chip.

公开(公告)号：US08390318B2

公开(公告)日：2013-03-05

申请号：US13401052

申请日：2012-02-21

申请人： Hideyuki Yokou ,  Takanori Eguchi ,  Manabu Ishimatsu

发明人： Hideyuki Yokou ,  Takanori Eguchi ,  Manabu Ishimatsu

IPC分类号： H03K17/16

CPC分类号： G11C29/022 ,  G11C29/028

摘要： Disclosed herein is a device that includes a replica buffer circuit that drives a calibration terminal, a reference-potential generating circuit that generates a reference potential, a comparison circuit that compares a potential appearing at the calibration terminal with the reference potential, and a control circuit that changes an output impedance of the replica buffer circuit based on a result of a comparison by the comparison circuit. The reference-potential generating circuit includes a first potential generating unit activated in response to an enable signal and a second potential generating unit activated regardless of the enable signal, and an output node of the first potential generating unit and an output node of the second potential generating unit are commonly connected to the comparison circuit.

摘要翻译： 本文公开了一种装置，其包括驱动校准端子的复制缓冲电路，产生参考电位的基准电位产生电路，将校准端子出现的电位与参考电位进行比较的比较电路和控制电路 其基于比较电路的比较结果来改变复制缓冲电路的输出阻抗。 参考电位产生电路包括响应于使能信号而被激活的第一电位产生单元和与使能信号无关地激活的第二电位产生单元，以及第一电位产生单元的输出节点和第二电位的输出节点 发电单元通常连接到比较电路。

公开(公告)号：US20120212286A1

公开(公告)日：2012-08-23

申请号：US13398711

申请日：2012-02-16

申请人： Hideyuki YOKOU ,  Isao Nakamura ,  Manabu Ishimatsu

发明人： Hideyuki YOKOU ,  Isao Nakamura ,  Manabu Ishimatsu

IPC分类号： G05F3/02

CPC分类号： H02M1/00 ,  H02M7/003 ,  H03K19/00361

摘要： Disclosed herein is a device that includes a bias line to which a bias current flows, a switch circuit controlling an amount of the bias current based on a control signal, a control line to which the control signal is supplied, and a cancellation circuit substantially cancelling a potential fluctuation of the bias line caused by changing the control signal, the potential fluctuation propagating via a parasitic capacitance between the control line and the bias line.

摘要翻译： 本文公开了一种装置，其包括偏置电流流过的偏置线，基于控制信号控制偏置电流量的开关电路，提供控制信号的控制线以及基本取消的取消电路 通过改变控制信号引起的偏置线的电位波动，通过控制线和偏置线之间的寄生电容传播的电位波动。

公开(公告)号：US20120212254A1

公开(公告)日：2012-08-23

申请号：US13401052

申请日：2012-02-21

申请人： Hideyuki YOKOU ,  Takanori Eguchi ,  Manabu Ishimatsu

发明人： Hideyuki YOKOU ,  Takanori Eguchi ,  Manabu Ishimatsu

IPC分类号： H03K19/003

CPC分类号： G11C29/022 ,  G11C29/028

摘要： Disclosed herein is a device that includes a replica buffer circuit that drives a calibration terminal, a reference-potential generating circuit that generates a reference potential, a comparison circuit that compares a potential appearing at the calibration terminal with the reference potential, and a control circuit that changes an output impedance of the replica buffer circuit based on a result of a comparison by the comparison circuit. The reference-potential generating circuit includes a first potential generating unit activated in response to an enable signal and a second potential generating unit activated regardless of the enable signal, and an output node of the first potential generating unit and an output node of the second potential generating unit are commonly connected to the comparison circuit.

摘要翻译： 本文公开了一种装置，其包括驱动校准端子的复制缓冲电路，产生参考电位的基准电位产生电路，将校准端子出现的电位与参考电位进行比较的比较电路和控制电路 其基于比较电路的比较结果来改变复制缓冲电路的输出阻抗。 参考电位产生电路包括响应于使能信号而被激活的第一电位产生单元和与使能信号无关地激活的第二电位产生单元，以及第一电位产生单元的输出节点和第二电位的输出节点 发电单元通常连接到比较电路。

公开(公告)号：US06898110B2

公开(公告)日：2005-05-24

申请号：US10416717

申请日：2001-10-19

申请人： Manabu Ishimatsu ,  Yoshihiko Inoue ,  Hiroshi Yoshioka ,  Masahito Suzuki

发明人： Manabu Ishimatsu ,  Yoshihiko Inoue ,  Hiroshi Yoshioka ,  Masahito Suzuki

IPC分类号： G11C29/00 ,  H01L23/528 ,  G11C5/06

CPC分类号： G11C29/70 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： In a device including regular circuits and redundant circuits, a plurality of relievable first wiring lines and a plurality of irrelievable second wiring lines are arranged in the same wiring layer as what constitutes the regular circuits and in the same direction, and at the same time the irrelievable wiring lines are arranged adjoining one another.

摘要翻译： 在包括常规电路和冗余电路的装置中，多个可解除的第一布线和多个不可绕线的第二布线布置在与正常电路和相同方向相同的布线层中，并且同时 不可相互连接的布线相互排列。

公开(公告)号：US06191983B1

公开(公告)日：2001-02-20

申请号：US09445964

申请日：1999-12-16

申请人： Goro Kitsukawa ,  Toshitsugu Ueda ,  Manabu Ishimatsu ,  Michihiro Mishima

发明人： Goro Kitsukawa ,  Toshitsugu Ueda ,  Manabu Ishimatsu ,  Michihiro Mishima

IPC分类号： G11C700

CPC分类号： G11C29/80 ,  G11C29/81 ,  G11C29/814 ,  H01L27/105 ,  H01L27/10897

摘要： There is provided a semiconductor memory which allows a redundant memory cell to be disposed at the center while maintaining the continuity of layout units of direct peripheral circuits and allows the total yield of the memory cell and the direct peripheral circuits to be improved. The inventive semiconductor memory is a 64 M-bits or 256 M-bits DRAM using a hierarchical word line structure or a multi-division bit line structure and comprises a main row decoder region, a main word driver region, a column decoder region, a peripheral circuit/bonding pad region, a memory cell array, a sense amplifier region, a sub-word driver region, intersection regions and the like formed on one semiconductor chip.

摘要翻译： 提供了一种半导体存储器，其允许将冗余存储器单元布置在中心，同时保持直接外围电路的布局单元的连续性，并且允许提高存储单元和直接外围电路的总产量。 本发明的半导体存储器是使用分层字线结构或多分割位线结构的64M位或256M位DRAM，并且包括主行解码器区域，主字驱动器区域，列解码器区域， 外围电路/焊盘区域，存储单元阵列，读出放大器区域，子字驱动器区域，交叉区域等形成在一个半导体芯片上。

公开(公告)号：US20140141543A1

公开(公告)日：2014-05-22

申请号：US14162671

申请日：2014-01-23

申请人： Akira Ide ,  MANABU ISHIMATSU ,  KENTARO HARA

发明人： Akira Ide ,  MANABU ISHIMATSU ,  KENTARO HARA

IPC分类号： H01L21/66

CPC分类号： H01L22/14 ,  G11C7/24 ,  G11C29/787 ,  G11C29/789 ,  G11C29/802 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for manufacturing a stacked semiconductor memory device includes testing a plurality of memory chips to detect first defective addresses, programming optical fuses with first defective address information on each of the plurality of memory chips that have the first defective addresses, stacking the plurality of memory chips, testing the stacked memory chips to detect second defective addresses, and programming electrical fuses with second defective address information.

摘要翻译： 一种用于制造叠层半导体存储器件的方法包括测试多个存储器芯片以检测第一缺陷地址，对具有第一缺陷地址的多个存储器芯片中的每一个上的第一缺陷地址信息编程光学熔丝，堆叠多个存储器 芯片，测试堆叠的存储器芯片以检测第二个缺陷地址，以及编程具有第二缺陷地址信息的电熔丝。

公开(公告)号：US08644086B2

公开(公告)日：2014-02-04

申请号：US13137849

申请日：2011-09-16

申请人： Akira Ide ,  Manabu Ishimatsu ,  Kentaro Hara

发明人： Akira Ide ,  Manabu Ishimatsu ,  Kentaro Hara

IPC分类号： G11C7/00

CPC分类号： H01L22/14 ,  G11C7/24 ,  G11C29/787 ,  G11C29/789 ,  G11C29/802 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a plurality of first chips, a second chip that controls the first chips, and internal wiring that connects the first chips and the second chip. The first chips each include: an optical fuse; a first latch circuit that retains information on the optical fuse; a second latch circuit that retains information on an electrical fuse, the information being supplied from the second chip through the internal wiring; and a select circuit that selects the information retained in either one of the first and second latch circuits. A redundancy determination signal is generated from the information selected. The information on the electrical fuse is transferred from the second chip to the first chips through the internal wiring.

摘要翻译： 半导体器件包括多个第一芯片，控制第一芯片的第二芯片和连接第一芯片和第二芯片的内部布线。 第一个芯片包括：一个光学保险丝; 第一锁存电路，其保存关于所述光学保险丝的信息; 第二锁存电路，其保存关于电熔丝的信息，所述信息通过所述内部布线从所述第二芯片提供; 以及选择电路，其选择保留在第一和第二锁存电路中的任一个中的信息。 从所选择的信息生成冗余确定信号。 电熔丝的信息通过内部布线从第二芯片传送到第一芯片。

公开(公告)号：US20120069685A1

公开(公告)日：2012-03-22

申请号：US13137849

申请日：2011-09-16

申请人： Akira Ide ,  Manabu Ishimatsu ,  Kentaro Hara

发明人： Akira Ide ,  Manabu Ishimatsu ,  Kentaro Hara

IPC分类号： G11C7/10

CPC分类号： H01L22/14 ,  G11C7/24 ,  G11C29/787 ,  G11C29/789 ,  G11C29/802 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a plurality of first chips, a second chip that controls the first chips, and internal wiring that connects the first chips and the second chip. The first chips each include: an optical fuse; a first latch circuit that retains information on the optical fuse; a second latch circuit that retains information on an electrical fuse, the information being supplied from the second chip through the internal wiring; and a select circuit that selects the information retained in either one of the first and second latch circuits. A redundancy determination signal is generated from the information selected. The information on the electrical fuse is transferred from the second chip to the first chips through the internal wiring.

摘要翻译： 半导体器件包括多个第一芯片，控制第一芯片的第二芯片和连接第一芯片和第二芯片的内部布线。 第一个芯片包括：一个光学保险丝; 第一锁存电路，其保存关于所述光学保险丝的信息; 第二锁存电路，其保存关于电熔丝的信息，所述信息通过所述内部布线从所述第二芯片提供; 以及选择电路，其选择保留在第一和第二锁存电路中的任一个中的信息。 从所选择的信息生成冗余确定信号。 电熔丝的信息通过内部布线从第二芯片传送到第一芯片。