公开(公告)号：US06809946B2

公开(公告)日：2004-10-26

申请号：US10443645

申请日：2003-05-22

申请人： Hiroki Fujisawa ,  Hideyuki Yokou

发明人： Hiroki Fujisawa ,  Hideyuki Yokou

IPC分类号： G11C502

CPC分类号： G11C7/1066 ,  G11C7/06 ,  G11C8/12 ,  G11C11/4091

摘要： In a semiconductor memory device including a bank equipped having a predetermined memory capacity, a sub amplifier block is disposed at a center of the bank divided into two sections. The sub amplifier block includes a plurality of sub amplifiers connected to sense amplifier sets disposed in the two memory regions through an LIO and a sub amplifier control circuit for controlling the sub amplifiers. If the sub amplifier control circuit selects a word line, a control operation is performed to activate only one side of the sub amplifiers positioned on both sides of the word line to thereby reduce the power consumed for activating the sub amplifiers.

摘要翻译： 在包括具有预定存储容量的存储体的半导体存储器件中，子放大器块设置在分为两部分的存储体的中心。 子放大器块包括通过LIO连接到设置在两个存储区域中的读出放大器组的多个子放大器和用于控制子放大器的子放大器控制电路。 如果副放大器控制电路选择字线，则执行控制操作以仅激活位于字线两侧的子放大器的一侧，从而减少用于激活子放大器的功耗。

公开(公告)号：US08952498B2

公开(公告)日：2015-02-10

申请号：US13434395

申请日：2012-03-29

申请人： Yasuyuki Shigezane ,  Hideyuki Yokou ,  Akira Ide

发明人： Yasuyuki Shigezane ,  Hideyuki Yokou ,  Akira Ide

IPC分类号： H01L29/40 ,  H01L23/48 ,  H01L23/00 ,  H01L25/065

CPC分类号： H01L23/481 ,  G11C5/025 ,  G11C5/063 ,  H01L24/13 ,  H01L24/14 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/13009 ,  H01L2224/13021 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/01047 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/05552

摘要： Disclosed herein is a device including a substrate and first and second chips stacked on the substrate. The first and second chips have penetration electrodes that are penetrating therethrough. Power terminals of the first and second chips are connected to each other and arranged in a first arrangement pitch. Signal terminals of the first and second chips are connected to each other and arranged in a second arrangement pitch that is smaller than the first arrangement pitch.

摘要翻译： 本文公开了一种包括衬底和堆叠在衬底上的第一和第二芯片的器件。 第一和第二芯片具有穿透其中的穿透电极。 第一芯片和第二芯片的电源端子彼此连接并以第一布置间距布置。 第一和第二芯片的信号端子彼此连接并且以比第一布置间距小的第二布置间距布置。

公开(公告)号：US20140241095A1

公开(公告)日：2014-08-28

申请号：US14270926

申请日：2014-05-06

申请人： Hideyuki Yokou

发明人： Hideyuki Yokou

IPC分类号： G11C5/14 ,  G11C11/4074

CPC分类号： G11C5/14 ,  G11C5/06 ,  G11C7/10 ,  G11C11/4074 ,  H01L25/00 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/13091 ,  H01L2924/15311 ,  H05K1/18 ,  H01L2924/00

摘要： To provide a semiconductor system including a plurality of core chips and an interface chip that controls the core chips. Each of the core chips includes an internal voltage generating circuit. The interface chip includes an unused chip information holding circuit that stores therein unused chip information of the core chips. The core chips respectively receive the unused chip information from the unused chip information holding circuit. When the unused chip information indicates an unused state, the internal voltage generating circuits are inactivated, and when the unused chip information indicates a used state, the internal voltage generating circuits are activated. With this configuration, unnecessary power consumption by the unused chips is reduced.

摘要翻译： 提供包括多个核心芯片的半导体系统和控制核心芯片的接口芯片。 每个核心芯片包括内部电压产生电路。 接口芯片包括未使用的芯片信息保持电路，其存储芯芯的未使用的芯片信息。 核心芯片分别从未使用的芯片信息保持电路接收未使用的芯片信息。 当未使用的芯片信息表示未使用状态时，内部电压产生电路被去激活，并且当未使用的芯片信息指示使用状态时，内部电压产生电路被激活。 利用这种配置，可以减少未使用芯片的不必要的功耗。

公开(公告)号：US20140286109A1

公开(公告)日：2014-09-25

申请号：US14295213

申请日：2014-06-03

申请人： Hideyuki YOKOU ,  Koji UEMURA ,  Manabu ISHIMATSU

发明人： Hideyuki YOKOU ,  Koji UEMURA ,  Manabu ISHIMATSU

IPC分类号： H03K19/00 ,  G11C11/4076 ,  G11C11/4093

CPC分类号： G11C11/4076 ,  G11C5/147 ,  G11C11/4093 ,  G11C29/022 ,  G11C29/028 ,  G11C2207/2254 ,  H03K17/167 ,  H03K19/0005 ,  H03K19/018571

摘要： A semiconductor device includes an output circuit having a plurality of unit buffer circuits, an impedance of each unit buffer circuit of the plurality of unit buffer circuits being adjustable, a control circuit configured to selectively activate one or more unit buffer circuits of the plurality of unit buffer circuits, and an impedance adjustment unit configured to adjust the impedance of each of the unit buffer circuits of the plurality of unit buffer circuits. The impedance adjustment unit includes a first power line, a replica circuit, and a load current generation circuit. The replica circuit and the load current generation circuit are coupled in common to the first power line, the replica circuit has a replica impedance that is substantially equal to the impedance of the output circuit, and the load current generation circuit changes current flowing therethrough.

摘要翻译： 半导体器件包括具有多个单元缓冲电路的输出电路，多个单元缓冲电路中的每个单元缓冲电路的阻抗是可调节的，控制电路被配置为选择性地激活多个单元中的一个或多个单元缓冲电路 缓冲电路和阻抗调整单元，被配置为调整多个单元缓冲电路中的每个单元缓冲电路的阻抗。 阻抗调整单元包括第一电力线，复制电路和负载电流产生电路。 复制电路和负载电流产生电路共同耦合到第一电力线，复制电路具有基本上等于输出电路的阻抗的复制阻抗，并且负载电流产生电路改变流过其中的电流。

公开(公告)号：US20080122450A1

公开(公告)日：2008-05-29

申请号：US11928459

申请日：2007-10-30

申请人： Hideyuki YOKOU

发明人： Hideyuki YOKOU

IPC分类号： G01R35/00

CPC分类号： G01R31/31713 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028

摘要： To include a first replica buffer that has substantially the same circuit configuration as a pull-up circuit which constitutes an output buffer and a second replica buffer that has substantially the same circuit configuration as a pull-down circuit which constitutes the output buffer. When a first calibration command ZQCS is issued, both a control signal ACT1 and ACT2 is activated, and a calibration operation is performed for both the first replica buffer and the second replica buffer in parallel.

摘要翻译： 包括具有与构成输出缓冲器的上拉电路基本相同的电路配置的第一复制缓冲器和具有与构成输出缓冲器的下拉电路基本相同的电路配置的第二复制缓冲器。 当发出第一校准命令ZQCS时，控制信号ACT1和ACT2都被激活，并且对第一复制缓冲器和第二复制缓冲器并行执行校准操作。

公开(公告)号：US08390318B2

公开(公告)日：2013-03-05

申请号：US13401052

申请日：2012-02-21

申请人： Hideyuki Yokou ,  Takanori Eguchi ,  Manabu Ishimatsu

发明人： Hideyuki Yokou ,  Takanori Eguchi ,  Manabu Ishimatsu

IPC分类号： H03K17/16

CPC分类号： G11C29/022 ,  G11C29/028

摘要： Disclosed herein is a device that includes a replica buffer circuit that drives a calibration terminal, a reference-potential generating circuit that generates a reference potential, a comparison circuit that compares a potential appearing at the calibration terminal with the reference potential, and a control circuit that changes an output impedance of the replica buffer circuit based on a result of a comparison by the comparison circuit. The reference-potential generating circuit includes a first potential generating unit activated in response to an enable signal and a second potential generating unit activated regardless of the enable signal, and an output node of the first potential generating unit and an output node of the second potential generating unit are commonly connected to the comparison circuit.

摘要翻译： 本文公开了一种装置，其包括驱动校准端子的复制缓冲电路，产生参考电位的基准电位产生电路，将校准端子出现的电位与参考电位进行比较的比较电路和控制电路 其基于比较电路的比较结果来改变复制缓冲电路的输出阻抗。 参考电位产生电路包括响应于使能信号而被激活的第一电位产生单元和与使能信号无关地激活的第二电位产生单元，以及第一电位产生单元的输出节点和第二电位的输出节点 发电单元通常连接到比较电路。

公开(公告)号：US20120262196A1

公开(公告)日：2012-10-18

申请号：US13439726

申请日：2012-04-04

申请人： Hideyuki YOKOU

发明人： Hideyuki YOKOU

IPC分类号： G01R31/3187

CPC分类号： G01R31/318513 ,  G11C5/02 ,  G11C29/023 ,  G11C29/025 ,  G11C29/14 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2924/1305 ,  H01L2924/00

摘要： Disclosed herein is a device includes first and second core chips and a test circuit. The first core chip outputs an internal signal to a second node thereof in response to a core-chip test signal supplied to a first node thereof. The second core chip outputs an internal signal to a second node thereof in response to the core-chip test signal supplied to a first node thereof. The test circuit generates test result signals based on the internal signal of the first core chip being output from the second node of the first core chip, and the internal signal of the second core chip being output from the third node of the first core chip.

摘要翻译： 本文公开了一种包括第一和第二核心芯片和测试电路的装置。 响应于提供给其第一节点的核心芯片测试信号，第一核心芯片将内部信号输出到其第二节点。 响应于提供给其第一节点的核心芯片测试信号，第二核心芯片将内部信号输出到其第二节点。 测试电路基于从第一核心芯片的第二节点输出的第一核芯片的内部信号，并且从第一核心芯片的第三节点输出第二核心芯片的内部信号，生成测试结果信号。

公开(公告)号：US20120212286A1

公开(公告)日：2012-08-23

申请号：US13398711

申请日：2012-02-16

申请人： Hideyuki YOKOU ,  Isao Nakamura ,  Manabu Ishimatsu

发明人： Hideyuki YOKOU ,  Isao Nakamura ,  Manabu Ishimatsu

IPC分类号： G05F3/02

CPC分类号： H02M1/00 ,  H02M7/003 ,  H03K19/00361

摘要： Disclosed herein is a device that includes a bias line to which a bias current flows, a switch circuit controlling an amount of the bias current based on a control signal, a control line to which the control signal is supplied, and a cancellation circuit substantially cancelling a potential fluctuation of the bias line caused by changing the control signal, the potential fluctuation propagating via a parasitic capacitance between the control line and the bias line.

摘要翻译： 本文公开了一种装置，其包括偏置电流流过的偏置线，基于控制信号控制偏置电流量的开关电路，提供控制信号的控制线以及基本取消的取消电路 通过改变控制信号引起的偏置线的电位波动，通过控制线和偏置线之间的寄生电容传播的电位波动。

公开(公告)号：US20120212254A1

公开(公告)日：2012-08-23

申请号：US13401052

申请日：2012-02-21

申请人： Hideyuki YOKOU ,  Takanori Eguchi ,  Manabu Ishimatsu

发明人： Hideyuki YOKOU ,  Takanori Eguchi ,  Manabu Ishimatsu

IPC分类号： H03K19/003

CPC分类号： G11C29/022 ,  G11C29/028

摘要： Disclosed herein is a device that includes a replica buffer circuit that drives a calibration terminal, a reference-potential generating circuit that generates a reference potential, a comparison circuit that compares a potential appearing at the calibration terminal with the reference potential, and a control circuit that changes an output impedance of the replica buffer circuit based on a result of a comparison by the comparison circuit. The reference-potential generating circuit includes a first potential generating unit activated in response to an enable signal and a second potential generating unit activated regardless of the enable signal, and an output node of the first potential generating unit and an output node of the second potential generating unit are commonly connected to the comparison circuit.

摘要翻译： 本文公开了一种装置，其包括驱动校准端子的复制缓冲电路，产生参考电位的基准电位产生电路，将校准端子出现的电位与参考电位进行比较的比较电路和控制电路 其基于比较电路的比较结果来改变复制缓冲电路的输出阻抗。 参考电位产生电路包括响应于使能信号而被激活的第一电位产生单元和与使能信号无关地激活的第二电位产生单元，以及第一电位产生单元的输出节点和第二电位的输出节点 发电单元通常连接到比较电路。

公开(公告)号：US08717839B2

公开(公告)日：2014-05-06

申请号：US13398702

申请日：2012-02-16

申请人： Hideyuki Yokou ,  Yasuyuki Shigezane

发明人： Hideyuki Yokou ,  Yasuyuki Shigezane

IPC分类号： G11C29/00 ,  G11C5/06 ,  G11C7/06 ,  G11C7/10 ,  G11C29/02

CPC分类号： G11C29/00 ,  G11C5/04 ,  G11C29/022 ,  G11C29/025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/00

摘要： Disclosed herein is a device that includes first and second current paths, first and second latch circuits electrically connected to the first and second current paths, respectively, a driver circuit supplying first data to the first latch circuit, and supplying second data representing a logical value opposite to a logical value of the first data to the second latch circuit, a control circuit controlling the driver circuit to be alternately and repeatedly in a first period in which the driver circuit supplies the first data to the first latch circuit and does not supply the second data to the second latch circuit, and in a second period in which the driver circuit supplies the second data to the second latch circuit and does not supply the first data to the first latch circuit, and a monitor circuit.

摘要翻译： 本文公开了一种包括第一和第二电流路径的装置，分别与第一和第二电流路径电连接的第一和第二锁存电路，向第一锁存电路提供第一数据的驱动电路，以及提供表示逻辑值的第二数据 与第一数据的逻辑值相对的第二锁存电路的控制电路，控制电路在驱动电路将第一数据提供给第一锁存电路的第一时段中交替重复地进行控制，并且不提供 第二数据到第二锁存电路，以及在第二周期中，驱动电路将第二数据提供给第二锁存电路，并且不向第一锁存电路提供第一数据，以及监视电路。