公开(公告)号：US06659352B1

公开(公告)日：2003-12-09

申请号：US09584542

申请日：2000-05-31

申请人： Hiroaki Asada ,  Joji Nakane ,  Tatsumi Sumi ,  Taketoshi Matsuura ,  Atsuo Inoue

发明人： Hiroaki Asada ,  Joji Nakane ,  Tatsumi Sumi ,  Taketoshi Matsuura ,  Atsuo Inoue

IPC分类号： G06K1906

CPC分类号： G06K19/0701 ,  G06K19/0723 ,  H02M2001/0022 ,  H02M2001/0025

摘要： A semiconductor integrated circuit which obtains a driving power from a carrier onto which data has been piggybacked, the semiconductor integrated circuit being characterized by demodulating data by correctly discriminating it even when the obtained power supply voltage has become overvoltage, and characterized by effectively using the power supplied by the carrier. The semiconductor integrated circuit includes: a two-voltage rectifier circuit as a power source circuit 111; a voltage regulator circuit 112 which exercises a control so that a power with a higher voltage (VDDH) used for demodulating data does not exceed a certain voltage value; a resistor 141; and a capacitor 142. With this construction, the voltage input to a regulator circuit 1121 as the reference voltage changes in correspondence to the change in voltage VDDH which is caused by the change in amplitude.

摘要翻译： 一种半导体集成电路，其从已经搭载数据的载体获得驱动电力，其特征在于，即使当所获得的电源电压已经变得过电压时，通过正确地识别数据来解调数据，并且其特征在于有效地使用电力 由承运人提供。 半导体集成电路包括：作为电源电路111的双电压整流电路; 电压调节器电路112，其进行控制，使得用于解调数据的具有较高电压（VDDH）的功率不超过一定电压值; 电阻器141; 和电容器142.通过这种结构，作为参考电压输入到调节器电路1121的电压对应于由振幅变化引起的电压VDDH的变化。

公开(公告)号：US06907088B1

公开(公告)日：2005-06-14

申请号：US09665133

申请日：2000-09-19

申请人： Joji Nakane ,  Tatsumi Sumi

发明人： Joji Nakane ,  Tatsumi Sumi

IPC分类号： G06K19/07 ,  H04B5/02 ,  H03D1/24 ,  H03D1/04

CPC分类号： G06K19/0723

摘要： In a contactless IC card that performs envelope detection on an ASK-modulated carrier wave and demodulates the carrier wave to recover data piggybacked thereon, demodulation is suspended during periods where there is no possibility of a change of a data value (from data 0 to data 1, or from data 1 to data 0) in the digital data piggybacked on the carrier wave. In so doing, incorrect data recovery can be prevented even when noise arises in power supply voltage waveform due to power consumption of an internal memory or the like.

摘要翻译： 在对ASK调制载波进行包络检测并对载波进行解调以恢复其背后的数据的非接触式IC卡中，在不存在数据值变化的可能性（从数据0到数据 1，或从数据1到数据0）载入载波上的数字数据。 这样做，即使由于内部存储器等的功耗而导致的电源电压波形中的噪声也能够防止错误的数据恢复。

公开(公告)号：US06747907B2

公开(公告)日：2004-06-08

申请号：US10307376

申请日：2002-12-02

申请人： Yoshitaka Mano ,  Joji Nakane

发明人： Yoshitaka Mano ,  Joji Nakane

IPC分类号： G11C1122

CPC分类号： G11C29/021 ,  G11C5/147 ,  G11C11/22 ,  G11C29/02 ,  G11C29/028 ,  G11C2029/5004

摘要： In a power supply voltage detection circuit using a reference potential generation circuit, as represented by a band gap reference circuit according to a prior art, the correction of dispersion in the detection level cannot be carried out after the completion of diffusion and assembly. Therefore, a power supply voltage detection circuit 4 is provided with a reference potential generation circuit 1, a divided voltage potential generation circuit 2 and a differential amplification circuit 3 for comparing the divided voltage potential to the reference potential. Furthermore, a ferroelectric memory 5 which stores correction data for correcting the reference potential, a data latch circuit 7 for storing correction data that has been read out, and a microcomputer logic unit 6 for controlling ferroelectric memory 5 as well as data latch circuit 7 are provided. The reference potential is altered according to correction data so that dispersion in the power supply voltage detection level is reduced.

摘要翻译： 在使用基准电位生成电路的电源电压检测电路中，如现有技术的带隙基准电路所示，在扩散组装完成后，不能进行检测水平的色散校正。 因此，电源电压检测电路4设置有参考电位产生电路1，分压电压产生电路2和差分放大电路3，用于将分压电位与参考电位进行比较。 此外，存储用于校正参考电位的校正数据的铁电存储器5，用于存储读出的校正数据的数据锁存电路7以及用于控制铁电存储器5以及数据锁存电路7的微计算机逻辑单元6， 提供。 参考电位根据校正数据而改变，使电源电压检测电平的偏差减小。

公开(公告)号：US6038160A

公开(公告)日：2000-03-14

申请号：US981441

申请日：1998-05-28

申请人： Joji Nakane ,  Nobuyuki Moriwaki

发明人： Joji Nakane ,  Nobuyuki Moriwaki

IPC分类号： G11C14/00 ,  G11C11/22 ,  H01L21/8242 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11502 ,  G11C11/22

摘要： A semiconductor memory device of nonvolatile ferroelectric capable of stable operation without loss of logic voltage "L" data of the memory cell in rewriting operation. To achieve, for example, as shown in FIG. 1, diodes 1, 2 are connected to cell plate lines 39, 40. Therefore, in rewriting operation, if there is a parasitic resistance 3 in the cell plate line 39, it is possible to prevent occurrence of transient phenomenon of temporary transition of the cell plate line 39 to an excessive negative voltage (for example, lower than -1V) which may cause loss of data.

摘要翻译： PCT No.PCT / JP97 / 01267 Sec。 371日期：1998年5月28日 102（e）日期1998年5月28日PCT 1997年11月4日PCT PCT。 公开号WO97 / 40500 PCT 日期：1997年10月30日一种不挥发性铁电体的半导体存储器件，能够在重写操作中不损失存储单元的逻辑电压“L”数据而稳定地操作。 为了实现，例如，如图1所示。 如图1所示，二极管1,2连接到单元板线39,40。因此，在重写操作中，如果在单元板线39中存在寄生电阻3，则可以防止发生临时转换的瞬态现象 电池板线39到可能导致数据丢失的过大的负电压（例如低于-1V）。