公开(公告)号：US06659352B1

公开(公告)日：2003-12-09

申请号：US09584542

申请日：2000-05-31

申请人： Hiroaki Asada ,  Joji Nakane ,  Tatsumi Sumi ,  Taketoshi Matsuura ,  Atsuo Inoue

发明人： Hiroaki Asada ,  Joji Nakane ,  Tatsumi Sumi ,  Taketoshi Matsuura ,  Atsuo Inoue

IPC分类号： G06K1906

CPC分类号： G06K19/0701 ,  G06K19/0723 ,  H02M2001/0022 ,  H02M2001/0025

摘要： A semiconductor integrated circuit which obtains a driving power from a carrier onto which data has been piggybacked, the semiconductor integrated circuit being characterized by demodulating data by correctly discriminating it even when the obtained power supply voltage has become overvoltage, and characterized by effectively using the power supplied by the carrier. The semiconductor integrated circuit includes: a two-voltage rectifier circuit as a power source circuit 111; a voltage regulator circuit 112 which exercises a control so that a power with a higher voltage (VDDH) used for demodulating data does not exceed a certain voltage value; a resistor 141; and a capacitor 142. With this construction, the voltage input to a regulator circuit 1121 as the reference voltage changes in correspondence to the change in voltage VDDH which is caused by the change in amplitude.

摘要翻译： 一种半导体集成电路，其从已经搭载数据的载体获得驱动电力，其特征在于，即使当所获得的电源电压已经变得过电压时，通过正确地识别数据来解调数据，并且其特征在于有效地使用电力 由承运人提供。 半导体集成电路包括：作为电源电路111的双电压整流电路; 电压调节器电路112，其进行控制，使得用于解调数据的具有较高电压（VDDH）的功率不超过一定电压值; 电阻器141; 和电容器142.通过这种结构，作为参考电压输入到调节器电路1121的电压对应于由振幅变化引起的电压VDDH的变化。

公开(公告)号：US06907088B1

公开(公告)日：2005-06-14

申请号：US09665133

申请日：2000-09-19

申请人： Joji Nakane ,  Tatsumi Sumi

发明人： Joji Nakane ,  Tatsumi Sumi

IPC分类号： G06K19/07 ,  H04B5/02 ,  H03D1/24 ,  H03D1/04

CPC分类号： G06K19/0723

摘要： In a contactless IC card that performs envelope detection on an ASK-modulated carrier wave and demodulates the carrier wave to recover data piggybacked thereon, demodulation is suspended during periods where there is no possibility of a change of a data value (from data 0 to data 1, or from data 1 to data 0) in the digital data piggybacked on the carrier wave. In so doing, incorrect data recovery can be prevented even when noise arises in power supply voltage waveform due to power consumption of an internal memory or the like.

摘要翻译： 在对ASK调制载波进行包络检测并对载波进行解调以恢复其背后的数据的非接触式IC卡中，在不存在数据值变化的可能性（从数据0到数据 1，或从数据1到数据0）载入载波上的数字数据。 这样做，即使由于内部存储器等的功耗而导致的电源电压波形中的噪声也能够防止错误的数据恢复。

公开(公告)号：US06246624B1

公开(公告)日：2001-06-12

申请号：US09198726

申请日：1998-11-24

申请人： Hiroshige Hirano ,  Kouji Asari ,  Tatsumi Sumi

发明人： Hiroshige Hirano ,  Kouji Asari ,  Tatsumi Sumi

IPC分类号： G11C700

CPC分类号： H03K17/223 ,  G01R19/0084 ,  G01R19/155 ,  G01R19/16538 ,  G06F1/28 ,  G11C5/143 ,  G11C8/08 ,  G11C11/22

摘要： The present invention comprises a first MOS transistor whose gate and drain are connected with a first node, a second MOS transistor whose gate and drain are connected with the first node and a third node, respectively, a first resistive element which is connected between the first node and a second node, a second resistive element which is connected between the second node and a ground voltage terminal, a first NOT circuit whose input terminal is connected with the second node, whose output terminal is a fourth node, and which is connected between the third node and the ground voltage terminal, and a second NOT circuit whose input terminal is connected with the fourth node and whose output terminal is a fifth node. Consequently, the present invention can detect voltage in a stable condition with low power consumption.

摘要翻译： 本发明包括栅极和漏极与第一节点连接的第一MOS晶体管，栅极和漏极分别与第一节点和第三节点连接的第二MOS晶体管，第一电阻元件连接在第一节点之间 节点和第二节点，连接在第二节点和地电压端子之间的第二电阻元件，其输入端与第二节点连接的第一NOT电路，其输出端子是第四节点，并且连接在 第三节点和地电压端子，以及第二NOT电路，其输入端与第四节点连接，其输出端为第五节点。 因此，本发明能够以低功耗检测稳定状态的电压。

公开(公告)号：US5953277A

公开(公告)日：1999-09-14

申请号：US037864

申请日：1998-03-10

申请人： Toshio Mukunoki ,  Hiroshige Hirano ,  George Nakane ,  Tetsuji Nakakuma ,  Tatsumi Sumi ,  Nobuyuki Moriwaki

发明人： Toshio Mukunoki ,  Hiroshige Hirano ,  George Nakane ,  Tetsuji Nakakuma ,  Tatsumi Sumi ,  Nobuyuki Moriwaki

IPC分类号： G11C14/00 ,  G11C5/14 ,  G11C7/06 ,  G11C7/14 ,  G11C7/22 ,  G11C11/22 ,  G11C11/401 ,  G11C7/02

CPC分类号： G11C11/22 ,  G11C5/147 ,  G11C7/06 ,  G11C7/14 ,  G11C7/22

摘要： A reference potential generator is constituted of two signal lines 21 and 22; a charge supplying circuit to supply charge to signal lines 21 and 22; a first connection circiut 24a and 24b connecting the charge supplying circuit 23 and two signal lines 21 and 22 in order to supply charge to the two signal lines; and a second connection circuit 25 connecting two signal lines 21 and 22 together by the second control signal, and two signal lines are disconnected after the potentials of the two signal lines determined by the supplied charge and each of load capacitances of signal lines are averaged. A semiconductor memory device of the invention incorporating the above reference potential generator generating an exact reference potential, is able to amplify and output the potential difference between the reference potential and the potential of data readout in the bit line, and by this, "1" or "0" of readout data can be precisely determined.

摘要翻译： 参考电位发生器由两条信号线21和22组成; 用于向信号线21和22提供电荷的充电提供电路; 连接充电电路23和两条信号线21和22的第一连接电路24a和24b，以向两条信号线提供电荷; 以及通过第二控制信号将两条信号线21和22连接在一起的第二连接电路25，在由所提供的电荷确定的两个信号线的电位和信号线的每个负载电容的平均值之后，两条信号线断开。 结合上述参考电位发生器产生精确参考电位的本发明的半导体存储器件能够放大并输出参考电位与位线中的数据读出电位之间的电位差，由此“1” 或读出数据的“0”。

公开(公告)号：US5546342A

公开(公告)日：1996-08-13

申请号：US322543

申请日：1994-10-13

申请人： George Nakane ,  Toshio Mukunoki ,  Nobuyuki Moriwaki ,  Tatsumi Sumi ,  Hiroshige Hirano ,  Tetsuji Nakakuma

发明人： George Nakane ,  Toshio Mukunoki ,  Nobuyuki Moriwaki ,  Tatsumi Sumi ,  Hiroshige Hirano ,  Tetsuji Nakakuma

IPC分类号： G11C14/00 ,  G11C7/10 ,  G11C11/22 ,  G11C7/00

CPC分类号： G11C7/1006

摘要： The life of a semiconductor memory device can be prolonged by using a plurality of memory cells and decreasing the stress applied to the dielectric film of the memory cells storing a data value "1." This is achieved in the present invention by decreasing the number of rewritings required to retain stored data. Specifically, the present invention utilizes a reverse and rewrite means to reverse and rewrite data back into memory cells after being read, memory means for memorizing a signal indicating whether the currently stored data is in a reversed state, and judging means for judging whether the data should be reversely output.

摘要翻译： 通过使用多个存储单元并减小施加到存储数据值“1”的存储单元的电介质膜的应力，可以延长半导体存储器件的寿命。 这通过减少保留存储数据所需的重写次数在本发明中实现。 具体地，本发明利用反向和重写装置在读取之后将数据反转并重写到存储器单元中，用于存储指示当前存储的数据是否处于反转状态的信号的存储装置，以及用于判断数据 应该反向输出。

公开(公告)号：US5282165A

公开(公告)日：1994-01-25

申请号：US696944

申请日：1991-05-08

申请人： Naomi Miyake ,  Tatsumi Sumi

发明人： Naomi Miyake ,  Tatsumi Sumi

IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/84

摘要： A random access memory includes a redundancy repair circuit having a plurality of parallel connected transistors and a plurality of fuses connected to respective drains of the plurality of transistors. An electrically resistive element is connected to a common node to reduce a difference in operating speeds between a first case in which the circuit is precharged from a state in which discharge to a low level was effected via one of the transistors and a case in which precharging of the circuit is effected from a state in which discharging was carried out via a plurality of the transistors.

摘要翻译： 随机存取存储器包括具有多个并联的晶体管的冗余修复电路和连接到多个晶体管的相应漏极的多个熔丝。 电阻元件连接到公共节点，以减少电路从其中经由晶体管中的一个导致放电到低电平的状态被预充电的第一情况之间的工作速度差，以及预充电的情况 的电路由经由多个晶体管进行放电的状态实现。

公开(公告)号：US07850086B2

公开(公告)日：2010-12-14

申请号：US10590994

申请日：2005-04-12

申请人： George Nakane ,  Tatsumi Sumi

发明人： George Nakane ,  Tatsumi Sumi

IPC分类号： G06K19/06

CPC分类号： G06K19/0701 ,  G06K19/0707 ,  G06K19/0712 ,  G06K19/0723

摘要： The present invention extends the reading range between a contactless type information medium (semiconductor integrated circuit) and a reader/writer, which exchanges data in contactless communications with the contactless type information medium, and enables a stable data exchange even if the power supply voltage is lowered when data is returned from the contactless type information medium to the reader/writer. Specifically, when data is returned from the contactless type information medium, the data to be returned is held in the logic circuit section 200 capable of operating at a lower voltage than the non-volatile memory circuit section 300, and the reset detection lower limit voltage to be used by the reset generating circuit 160 during the data-returning period is set to be lower than that during periods other than the data-returning period.

摘要翻译： 本发明扩大了在非接触式信息介质（半导体集成电路）和读取器/写入器之间的读取范围，该读取器/写入器与非接触式信息介质进行非接触式通信中的数据，并且即使电源电压为 当从非接触式信息介质返回到读取器/写入器时降低。 具体地说，当从非接触式信息介质返回数据时，要返回的数据被保持在能够以比非易失性存储器电路部分300更低的电压工作的逻辑电路部分200中，并且复位检测下限电压 在数据返回期间由复位生成电路160使用的数据被设定为低于数据返回期间以外的期间。

公开(公告)号：US07011252B2

公开(公告)日：2006-03-14

申请号：US10821979

申请日：2004-04-12

申请人： Mitsuyoshi Ohya ,  Tatsumi Sumi

发明人： Mitsuyoshi Ohya ,  Tatsumi Sumi

IPC分类号： G06K19/06 ,  G06K5/00

CPC分类号： G06K7/0008 ,  G06F9/441 ,  G06K19/0719 ,  G06K19/0723

摘要： In an IC card applicable to a plurality of data transfer methods and including a plurality of OSs, when power sufficient for the operation is supplied to the IC card, an initial OS selecting section activates one of the plural OSs as an initial OS on the basis of identification information stored in a nonvolatile memory. A transfer method determining section determines a data transfer method on the basis of data received from a reader/writer. An OS applicability determining section determines whether or not the determined data transfer method accords with a data transfer method corresponding to the currently employed OS. When the data transfer methods do not accord with each other, an OS switching section switches the currently employed OS to another OS.

摘要翻译： 在适用于多个数据传输方法并且包括多个OS的IC卡中，当对IC卡提供足够的操作的电力时，初始OS选择部分基于原始OS激活多个OS中的一个作为初始OS 存储在非易失性存储器中的识别信息。 传送方法确定部分基于从读取器/写入器接收的数据来确定数据传送方法。 OS适用性确定部分确定所确定的数据传输方法是否符合与当前使用的OS相对应的数据传输方法。 当数据传输方法彼此不一致时，OS切换部分将当前使用的OS切换到另一OS。

公开(公告)号：US5523974A

公开(公告)日：1996-06-04

申请号：US344680

申请日：1994-11-21

申请人： Hiroshige Hirano ,  George Nakane ,  Tetsuji Nakakuma ,  Nobuyuki Moriwaki ,  Toshio Mukunoki ,  Tatsumi Sumi

发明人： Hiroshige Hirano ,  George Nakane ,  Tetsuji Nakakuma ,  Nobuyuki Moriwaki ,  Toshio Mukunoki ,  Tatsumi Sumi

IPC分类号： G11C11/401 ,  G11C11/22 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/789

摘要： A semiconductor memory device comprises a main memory cell, a redundant memory cell, a redundant address data cell comprising a non-volatile memory which electrically memorizes an address of a redundant memory cell which replaced a failed memory cell in the main memory cell, a control circuit 15 and a redundant memory cell selecting circuit 16. The redundant memory cell selecting circuit serves to hold first address data which has been read from the redundant address data cell, and to compare the first address data with second address data for a read or write operation which is input via the control circuit and thereby select the main memory cell or the redundant memory cell.

摘要翻译： 半导体存储器件包括主存储器单元，冗余存储器单元，冗余地址数据单元，其包括非易失性存储器，其电存储代替主存储单元中的故障存储器单元的冗余存储器单元的地址;控制器 电路15和冗余存储单元选择电路16.冗余存储单元选择电路用于保存从冗余地址数据单元读取的第一地址数据，并将第一地址数据与用于读或写的第二地址数据进行比较 通过控制电路输入的操作，从而选择主存储单元或冗余存储单元。

公开(公告)号：US5430671A

公开(公告)日：1995-07-04

申请号：US224589

申请日：1994-04-07

申请人： Hiroshige Hirano ,  Tatsumi Sumi ,  Yoshihisa Nagano

发明人： Hiroshige Hirano ,  Tatsumi Sumi ,  Yoshihisa Nagano

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A semiconductor memory device comprising bit line, word line, plate electrode, ferroelectric capacitor having first electrode and second electrode, said second electrode being coupled to said plate electrode, MOS transistor the source of which is coupled to said first electrode, the gate is coupled to said word line and the drain is coupled to said bit line, and adjusting capacitor for adjusting bit line capacitance coupled to said bit line. The adjusting capacitor is provided to increase the potential difference for reading and control occurrence of operating errors.

摘要翻译： 一种半导体存储器件，包括位线，字线，平板电极，具有第一电极和第二电极的铁电电容器，所述第二电极耦合到所述平板电极，MOS晶体管的源极耦合到所述第一电极，栅极耦合 到所述字线，并且所述漏极耦合到所述位线，以及调整电容器，用于调整耦合到所述位线的位线电容。 提供调整电容器以增加用于读取和控制操作错误发生的电位差。