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公开(公告)号：US20120221679A1
公开(公告)日：2012-08-30
申请号：US13403076
申请日：2012-02-23
IPC分类号： G06F15/16
CPC分类号： G06F13/20 , G06F5/065 , G06F13/26 , G06F13/32 , G06F13/385 , G06F2205/065
摘要： Between a CPU and a communication module, a write buffer, a write control section, a read buffer and a read control section are provided. The CPU directly accesses and the write buffer and the read buffer. By periodically outputting a communication request, the read control section reads data, which the communication module received from other nodes, and transfers the data to the read buffer. The write control section transfers to the communication module the data written in the write buffer as transmission data. In addition, a bypass access control section and an access sequence control section are provided. The bypass access control section controls direct data read and data write between the CPU and the communication module. The access sequence control section controls sequence of accesses of the control sections to the communication module.
摘要翻译： 在CPU和通信模块之间，提供写入缓冲器，写入控制部分，读取缓冲器和读取控制部分。 CPU直接访问写缓冲区和读缓冲区。 通过周期性地输出通信请求，读取控制部分读取通信模块从其他节点接收的数据，并将数据传送到读取缓冲器。 写入控制部分将写入缓冲器中的数据作为传输数据传送给通信模块。 另外，提供了旁路接入控制部和接入序列控制部。 旁路访问控制部分控制CPU和通信模块之间的直接数据读取和数据写入。 访问序列控制部分控制对通信模块的控制部分的访问顺序。
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公开(公告)号：US09015272B2
公开(公告)日：2015-04-21
申请号：US13403076
申请日：2012-02-23
CPC分类号： G06F13/20 , G06F5/065 , G06F13/26 , G06F13/32 , G06F13/385 , G06F2205/065
摘要： Between a CPU and a communication module, a write buffer, a write control section, a read buffer and a read control section are provided. The CPU directly accesses and the write buffer and the read buffer. By periodically outputting a communication request, the read control section reads data, which the communication module received from other nodes, and transfers the data to the read buffer. The write control section transfers to the communication module the data written in the write buffer as transmission data. In addition, a bypass access control section and an access sequence control section are provided. The bypass access control section controls direct data read and data write between the CPU and the communication module. The access sequence control section controls sequence of accesses of the control sections to the communication module.
摘要翻译： 在CPU和通信模块之间，提供写入缓冲器，写入控制部分，读取缓冲器和读取控制部分。 CPU直接访问写缓冲区和读缓冲区。 通过周期性地输出通信请求，读取控制部分读取通信模块从其他节点接收的数据，并将数据传送到读取缓冲器。 写入控制部分将写入缓冲器中的数据作为传输数据传送给通信模块。 另外，提供了旁路接入控制部和接入序列控制部。 旁路访问控制部分控制CPU和通信模块之间的直接数据读取和数据写入。 访问序列控制部分控制对通信模块的控制部分的访问顺序。
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公开(公告)号：US20080052555A1
公开(公告)日：2008-02-28
申请号：US11878799
申请日：2007-07-26
IPC分类号： G06F1/06
CPC分类号： G06F1/3203 , G06F1/28 , G06F1/3237 , Y02D10/126 , Y02D10/128
摘要： A microcomputer includes a main oscillator for generating and outputting a main clock signal, a sub oscillator for generating and outputting a sub clock signal, a central processing unit that operates based on the main clock signal, a signal output circuit that operates based on the sub clock signal and outputs a timing signal at a predetermined interval, and a voltage monitoring circuit that operates based on the sub clock signal and intermittently performs a voltage monitoring function in response to the timing signal. The sub oscillator operates independently of the main oscillator.
摘要翻译： 微型计算机包括用于产生和输出主时钟信号的主振荡器，用于产生和输出子时钟信号的子振荡器，基于主时钟信号操作的中央处理单元，基于子时钟信号操作的信号输出电路 时钟信号并以预定间隔输出定时信号，以及电压监视电路，其基于子时钟信号进行操作，并且响应于定时信号间歇地执行电压监视功能。 子振荡器独立于主振荡器工作。
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公开(公告)号：US20090106572A1
公开(公告)日：2009-04-23
申请号：US12285481
申请日：2008-10-07
IPC分类号： G06F1/08
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3293 , Y02D10/122 , Y02D10/126
摘要： A sub-microcomputer having a sub-CPU and a power supply control section that controls the power supply to a main microcomputer is disposed in addition to the main microcomputer having a main CPU. A sub-clock section that supplies a sub-clock signal having a lower frequency to the sub-microcomputer can change over between a continuous mode and an intermittent mode. When the main CPU gives an operation stop notification to the sub-CPU, the sub-CPU recognizes the notification, stops the power supply to the main microcomputer, and sets the sub-clock section to the intermittent mode. The sub-CPU determines that the operation state condition is satisfied in the period of the intermittent mode, the sub-CPU changes over the sub-clock section to the continuous mode to restart the power supply to the main microcomputer.
摘要翻译： 除了具有主CPU的主微型计算机之外，还配置有具有子CPU和控制对主微型计算机的电力供应的电源控制部的子微型计算机。 向子微型计算机提供具有较低频率的子时钟信号的子时钟部分可以在连续模式和间歇模式之间切换。 当主CPU向子CPU发出操作停止通知时，子CPU识别通知，停止对主微型计算机的供电，并将子时钟部分设置为间歇模式。 子CPU确定在间歇模式的周期内操作状态条件满足，子CPU将副时钟部分切换为连续模式，以重新开始向主微型计算机供电。
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5.发明申请公开(公告)号：US20080303497A1
公开(公告)日：2008-12-11
申请号：US12076451
申请日：2008-03-19
IPC分类号： G05F1/00
CPC分类号： G05F1/56
摘要： A semiconductor integrated circuit device for controlling an external output transistor is provided. The semiconductor integrated circuit device comprises: a first power supply circuit including an output circuit and providing a first series regulator in cooperation with the output external transistor; and a plurality of terminals. The plurality of terminals includes a control signal output terminal and high and low electric potential side power supply terminals for supplying electric power to the first power supply circuit. At least one of the high and low electric potential side power supply terminals is arranged adjacent to the control signal output terminal and defined as a first terminal. Short-circuiting between the control signal output terminal and the first terminal causes the external output transistor to switch into an off state.
摘要翻译： 提供一种用于控制外部输出晶体管的半导体集成电路器件。 所述半导体集成电路装置包括：第一电源电路，包括输出电路，并与所述输出外部晶体管配合提供第一串联调节器; 和多个终端。 多个端子包括用于向第一电源电路供电的控制信号输出端子和高低电位侧电源端子。 高电压侧电源端子和低电位侧电源端子中的至少一个被配置为与控制信号输出端子相邻并被定义为第一端子。 控制信号输出端子与第一端子之间的短路导致外部输出晶体管切换到断开状态。
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公开(公告)号：US08046615B2
公开(公告)日：2011-10-25
申请号：US12285481
申请日：2008-10-07
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3293 , Y02D10/122 , Y02D10/126
摘要： A sub-microcomputer having a sub-CPU and a power supply control section that controls the power supply to a main microcomputer is disposed in addition to the main microcomputer having a main CPU. A sub-clock section that supplies a sub-clock signal having a lower frequency to the sub-microcomputer can change over between a continuous mode and an intermittent mode. When the main CPU gives an operation stop notification to the sub-CPU, the sub-CPU recognizes the notification, stops the power supply to the main microcomputer, and sets the sub-clock section to the intermittent mode. The sub-CPU determines that the operation state condition is satisfied in the period of the intermittent mode, the sub-CPU changes over the sub-clock section to the continuous mode to restart the power supply to the main microcomputer.
摘要翻译： 除了具有主CPU的主微型计算机之外，还配置有具有子CPU和控制对主微型计算机的电力供应的电源控制部的子微型计算机。 向子微型计算机提供具有较低频率的子时钟信号的子时钟部分可以在连续模式和间歇模式之间切换。 当主CPU向子CPU发出操作停止通知时，子CPU识别通知，停止对主微型计算机的供电，并将子时钟部分设置为间歇模式。 子CPU确定在间歇模式的周期内操作状态条件满足，子CPU将副时钟部分切换为连续模式，以重新开始向主微型计算机供电。
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7.发明授权公开(公告)号：US07906946B2
公开(公告)日：2011-03-15
申请号：US12076451
申请日：2008-03-19
IPC分类号： G05F1/00
CPC分类号： G05F1/56
摘要： A semiconductor integrated circuit device for controlling an external output transistor is provided. The semiconductor integrated circuit device comprises: a first power supply circuit including an output circuit and providing a first series regulator in cooperation with the output external transistor; and a plurality of terminals. The plurality of terminals includes a control signal output terminal and high and low electric potential side power supply terminals for supplying electric power to the first power supply circuit. At least one of the high and low electric potential side power supply terminals is arranged adjacent to the control signal output terminal and defined as a first terminal. Short-circuiting between the control signal output terminal and the first terminal causes the external output transistor to switch into an off state.
摘要翻译： 提供一种用于控制外部输出晶体管的半导体集成电路器件。 所述半导体集成电路装置包括：第一电源电路，包括输出电路，并与所述输出外部晶体管配合提供第一串联调节器; 和多个终端。 多个端子包括用于向第一电源电路供电的控制信号输出端子和高低电位侧电源端子。 高电压侧电源端子和低电位侧电源端子中的至少一个被配置为与控制信号输出端子相邻并被定义为第一端子。 控制信号输出端子与第一端子之间的短路导致外部输出晶体管切换到断开状态。
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公开(公告)号：US07900081B2
公开(公告)日：2011-03-01
申请号：US11878799
申请日：2007-07-26
IPC分类号： G06F1/04
CPC分类号： G06F1/3203 , G06F1/28 , G06F1/3237 , Y02D10/126 , Y02D10/128
摘要： A microcomputer includes a main oscillator for generating and outputting a main clock signal, a sub oscillator for generating and outputting a sub clock signal, a central processing unit that operates based on the main clock signal, a signal output circuit that operates based on the sub clock signal and outputs a timing signal at a predetermined interval, and a voltage monitoring circuit that operates based on the sub clock signal and intermittently performs a voltage monitoring function in response to the timing signal. The sub oscillator operates independently of the main oscillator.
摘要翻译： 微型计算机包括用于产生和输出主时钟信号的主振荡器，用于产生和输出子时钟信号的子振荡器，基于主时钟信号操作的中央处理单元，基于子时钟信号操作的信号输出电路 时钟信号并以预定间隔输出定时信号，以及电压监视电路，其基于子时钟信号进行操作，并且响应于定时信号间歇地执行电压监视功能。 子振荡器独立于主振荡器工作。
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